CMOS Interview Questions Part 1

Q1. What is the threshold voltage of a MOS transistor? How it varies with the body bias?

Q2. What is channel length modulation effect? How the voltage current characteristics are affected because of this effect?

Q3. What is body effect? How does it influence the threshold voltage of a MOS transistor?

Q4. What is trans conductance of a MOS transistor? Explain its role in the operation of the transistor.

Q5. How one NMOS and one PMOS transistor are combined to behave like an ideal switch.

Q6. Draw the ideal characteristics of a CMOS inverter and compare it with the actual characteristics.

Q7. What is noise margin?

• The minimum amount of noise that can be allowed on the input stage that output will not affected.

Q8. What is the inversion voltage of an inverter?
Q9. How the inversion voltage is affected by the relative sizes of the sizes of the NMOS and PMOS transistors of the CMOS transistors of the CMOS inverter?

Q10. Find out the noise margin of a CMOS inverter.
Q11. What are the various ways to reduce the delay time of a CMOS inverter?

Q12. Implement the equation X = ((A’ + B’) (C’ + D’ + E’) + F’) G’ using complementary CMOS.
Q13. Explain sizing of the inverter?
Q14. What happens to delay if you increase load capacitance?

• Delay increases

Q15. What is Body Effect?

• When the substrate of a NMOS or PMOS is not connected to the source, there exists a bias voltage Vsb across the source and substrate.

Q16. Why PMOS and NMOS are sized equally in a Transmission Gates?
Q17. What is latch up in CMOS?

• Latch is the formation of a low-impedance path in CMOS between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and the ground rail.

Q18. What is the average static power consumption if, at any time, each input turns on with an(independent) probability of 0.1?

Q19. Explain dynamic power dissipation in CMOS?

• Each time the capacitor gets charged through the PMOS transistor, its voltage rises from 0 to VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the high-to-low transition, this capacitor discharged, and the stored energy is dissipated in the NMOS transistor.
• P=αCLVDD^2f

Q20. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Q21. What is Charge Sharing?

Q22. Why don't we use just one NMOS or PMOS transistor as a transmission gate?

• PMOS degrades Logic 0 & NMOS degrades logic 1
• To restore the logic levels to full, both NMOS & PMOS will be used together in TG.

Q23. What are the limitations in increasing the power supply to reduce delay

• More power consumption

Q24. Draw the stick diagram of a NAND gate.

Q25. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

Q26. What is the fundamental difference between a MOSFET and BJT?

• In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes (p-channel MOS)
• In BJT, we see current due to both the carrier’s electrons and holes.
• BJT is a current controlled device and MOSFET is a voltage controlled device.

Q27. What is clock feed through?

Q28. In CMOS technology, why do we design the size of PMOS to be higher than the NMOS?

• In PMOS the carriers are holes whose mobility is less than the electrons, the carriers in NMOS.  So PMOS is slower than NMOS.
• In CMOS technology, NMOS helps in pulling down the output to ground and PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node.
• If we have a larger PMOS then there will be more carriers to charge the node fast.
• We do this to get equal rise and fall times for the output node.

Q29. For a CMOS inverter, the transition slope of Vout vs Vin DC characteristics can be increased (steeper transition) by.

• Increasing W/L of both transistors by the same factor

Q30. Design buffer and inverter using XOR gates.
Click here for part 2

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Hi I’m Designer of this blog.