What is
Design for Testability (DFT)?
We have a test control from outside. Once it is configured as the shift register, we can feed some data from outside from my SCANIN pin, and we can serially shift the data to all the flip flops. Similarly if we apply clocks the shift register data will be shifted out from this SCANOUT pin, so we can observe the states of the flip flops also. So, this is the basic idea how we are solving the controllability and observe ability problems.
Scan Design Rules
- DFT is a technique that makes test generation and test application easier and cost effective.
- In testing of sequential circuits it is difficult to control and observe the internal flops.
- DFT techniques help in making the internal flip-flop easily controllable and observable.Controllable means you can initialize them into any value you want and observable means we can read out their values whenever we want.Basically converts the sequential circuit test generation problem to combinational circuit test generation problem.
DFT
Techniques
DFT
techniques classified into two types
Ad-hoc
technique
- Ad-hoc, they are a collection of techniques a long list of do’s and don’ts. So, some experienced designers they have provided a list, that you should not get a clock you should not do this, you should not do that. So, if you follow those rules, then your circuit will be a little better from the testing point of view.
Structured
technique
- Scan path
- Partial scan
- Level sensitive scan design
Scan Path
Design technique
- This is one of the most widely used technique.
- In this technique we take a conventional sequential circuit we call it a non-scan sequential circuit. So, we can modify this circuit using an automated tool very easily to insert scan path.
 |
| Sequential circuit |
What we are actually doing:
- All the flip-flops are replaced by scan flip-flops. Scan flip flop is essentially a D flip flop with a 2 to 1 multiplexer before it.
- Connect the scan flip-flops as configurable shift register.
- Add one test control primary input.
- Add a SCANIN input and SCANOUT for the shift register.
 |
| Scan Flip Flop |
We have a test control from outside. Once it is configured as the shift register, we can feed some data from outside from my SCANIN pin, and we can serially shift the data to all the flip flops. Similarly if we apply clocks the shift register data will be shifted out from this SCANOUT pin, so we can observe the states of the flip flops also. So, this is the basic idea how we are solving the controllability and observe ability problems.
- If TC=1 (Normal Mode) MUX selects D.
- If TC=0 (Test Mode) MUX selects SD.
 |
| Scan Inserted Sequential Circuit |
Scan Design Rules
- A set of rules that must be confirmed during design
- Use only clocked D flip flops to implement storage elements.
- At least one primary input pin must be available for test.
- Clock signal must not feed data inputs to flip-flops.
- All clocks must be directly fed from inputs, so that scan flip flops can work properly in scan register mode.
Scan and performance
overheads
- Area overhead
- Gate overhead = [4ns/ (ng+10ns)] x 100%
- ns = number of flip flop
- ng = number of gates in combinational logic.
Multiplexer delay added in
combinational path
- Flip flop replaced by Scan flip flop
Flip flop output loading due
to one additional fan-out.
- Scan flip flop output driving two inputs instead of one.
We have seen that we are
using some additional hardware and additional time, significantly additional
time to address the problem of testing sequential circuits. Typically 5-6%
degradation occurs but this additional time and performance degradation is acceptable otherwise
it is impossible to test these types of circuits. So, design for testability
(DFT) is very important technique.
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