What is Built In Self Test (BIST)?
- BIST is a design-for-testability technique that places the testing functions physically with the circuit under test (CUT).
- BIST is considered as one of the most promising solution for memory testing. The basic idea of BIST, in its most simple form, is to design a circuit so that the circuit can test itself and determine whether it is faulty or fault free.
- The basic BIST architecture requires the addition of three hardware blocks to a digital circuit: a test pattern generator, a comparator, and a test controller. The test pattern generator generates the test patterns for the CUT.
BIST Architecture |
This typically requires that
additional circuitry and functionality be incorporated into the design of the
circuit to facilitate the self-testing feature. This additional functionality
must be capable of generating test patterns as well as providing a mechanism to
determine if the output responses of the memory under test to the test patterns
correspond to that of a fault-free circuit. The main feature of the MBIST is
the capability to test memory through an in- built algorithm.
- The built-in self-test employed for memories is known as MBIST (Memory Built-In Self-Test). The MBIST logic may be capable of running memory testing algorithms to verify memory functionality and memory faults.
BIST has the following
advantages:
- Low of cost
- At-speed testing
- Easy memory access for testing
Due to these advantages, MBIST has
become the most preferred technique to test the embedded memories. As MBIST is
an additional hardware to test the memory, it requires an additional area on
the chip.
Memory Built In Self Test (MBIST)
- Due to the complexity of memory architectures, the possibility of occurring manufacturing defects is more. Hence, memory testing is a very challenging task.
- Memory Built-in self-test (MBIST) has been proven to be one of the most cost-effective and widely used solutions for memory testing.
- The architecture of Memory built-in self-test is shown in the Figure. MBIST consists of a controller, Background pattern generator, address generator, write/read control signal and a memory with its wrapper.
- Background generator is the data generator which generates the data to be written to memory. The address generator is to generate an address for memory to access the cell for performing read/write operations.
- A comparator is to check the data read from the memory during a read operation with the golden data. If they are different there is a fault.
- A controller is to provide control signals to address generator, background generator and read/write signal.
The memory will operate in 2
modes.
1. Test Mode
2. Normal Mode
A multiplexer is used to select
the inputs based on the selection line. In test mode, the multiplexer selects
the address generator and background generator of the BIST architecture. In
normal mode, the multiplexer selects the address and data sent by the processor.
The BIST architecture comprises of:
1. BIST
Controller
- The BIST controller provides the control signals to the address and data generator and a write/read signal to the memory.
2. Address
Generator :The address generator can be
design with 3 pattern generators.
- Binary counter
- Gray counter
- Linear Feedback Shift Register (LFSR)
3. Data
Generator
- The Data generator generates the data for memory to perform a write operation by using the control signals provided by the controller.
4. FSM (for
control signal)
- The FSM in the BIST controller is to provide write/read signal.
- It allows for robust testing of memories
- Lesser test cost
- Reduced test time
- All the memories of the design can be tested in parallel
- Increase in area. However, this increase in area is very small as comparison to the benefits it provides.
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