What is Timing borrowing concept?
The time borrowing technique, is also called cycle stealing, occurs at a latch.
- In a latch, one edge of the clock makes the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input;this clock edge is called the opening edge.
- The second edge of the clock closes the latch, that is, any change on the data input is no longer available at the output of the latch; this clock edge is called the closing edge.
- The unique property which enables above advantages is time borrowing.
- A level-sensitive latch is transparent for the duration of an active clock pulse. Time borrowing technique can relax the normal edge-to-edge timing requirements of synchronous designs.
- A combinational path which is long enough and is determining the maximum frequency of the design can borrow some time from a shorter path in subsequent latch-to-latch stages to meet its timing.
What does SDC constraint file contains?
SDC stands for synopsys design constraints. SDC is a format used to specify the design timing, power and area constraints. SDC is tcl based.
Types of information
- Operating Conditions
- Multi voltage and power optimization constraints
set_max_dynamic_power
set_max_leakage_power
set_level_shifter_threshold
- wire load models
set_wire_load_mode
set_wire_load_model
set_wire_load_selection_group
- system interface
set_driving_cell
set_fanout_load
set_input_transition
set_load
set_port_fanout_number
- design rule constraints
set_max_capacitance
set_min_capacitance
set_max_fanout
set_max_transition
- timing constraints
create_generated_clock
group_path
set_clock_gating_check
set_clock_groups
set_clock_latency
set_clock_sense
set_clock_transition
set_clock_uncertainty
set_data_check
set_disable_timing
set_ideal_latency
set_ideal_network
set_ideal_transition
set_input_delay
set_max_time_borrow
set_output_delay
set_propagated_clock
set_resistance
set_timing_derate
- area constraints
- timing exceptions
set_max_delay
set_min_delay
set_multi cycle_path
- logic assignments
set_logic_dc
set_logic_one
set_logic_zero
In A Reg To Reg Path If You Have Setup Problem Where Will You Insert Buffer-near to Launching Flop Or Capture Flop? Why?
- Near to capture path.
- Because there may be other paths passing through or originating from the flop nearer to launch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degrade. If all those paths have violation then we may insert buffer nearer to launch flop provided it improves slack.
What are various Timing Optimization Techniques used by tool during place optimization?
Timing Optimization Techniques
- Mapping
- Unmapping
- Pin Swapping
- Buffering
- Cell Sizing
- Cloning
- Logic Restructuring
What is cloning and buffering?
- Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.
- Buffering is a method of optimization that is used to insert buffers in high fan-out nets to decrease the delay
What are high fan out nets(HFN's)?how do they differ from other nets?
- HFN's are the nets which drives more number of load as compared to other nets. we set some max fan out limit by using set_max_fanout.
- The nets which have greater than these limits are considered as HFN's.
- Example Clock, Set/Reset, Scan Enable nets are high fan-out nets.
What is logic restructuring?
- Logic restructuring means to rearrange logic to meet timing constraints on critical paths of design.
- Move high switching operations up in the logic cone and low switching operations back in the logic cone; a gate-level dynamic power optimization technique.
- In design with low-power intent, synthesis tools automatically perform a variety of power optimization techniques including logic restructuring.
- It reduce three stages to two stages through logic equivalence transformation, so the circuit has less switching and fewer transitions.
- On a sample of designs, logic restructuring reduced dynamic power by less than 5%. It had no significant impact on any other aspects of the design flow.
Define (a) setup time (b) hold time (c) clock to Q delay.
- Setup time: Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock.
- Hold time: The hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data is reliably sampled by the clock.
- Clock to Q delay: The clock to Q delay is the amount of the propagation time required for the data signal to reach the output (Q) of the flip flop after the clock event.
Explain Synopsys Prime Time flow.
- set library path
set link_path
- read the design
- link library and the design
- add design constraints (read_sdc)
- add constant value to input port (for timing simulation)
- report_constraints
- report_timing
Delay Calculation of each timing path:
STA calculates the delay along each timing path by determining the Gate delay and Net
delay.
Gate Delay: Amount of delay from the input to the output of a logic gate. It is calculated
based on two parameters
- Input Transition Time
- Output Load Capacitance
Net Delay: Amount of delay from the output of a gate to the input of the next gate in a
timing path. It depends on the following parameters
- Parasitic Capacitance
- Resistance of net
Define negative setup and hold time.
- Negative Setup time: In certain cases, due to the excessive delay (example: caused by lot of inverters in the clock path) on the clock signal, the clock signal actually arrives later than the data signal. The actual clock edge you want your data to latch arrives later than the data signal. This is called negative set up time.
- Negative Hold time: It basically allows the data that was supposed to change in the next cycle, change before the present clock edge.
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