Q1. Write a Verilog code using behavioral modeling for a 4-bit shift register?
Q2. Write a Verilog code for positive edge
triggered D-flip flop with (a) synchronous reset and (b) asynchronous reset.
Q3.
Describe the difference between the system tasks $monitor and $display?
Q4.
List the differences between tasks and functions.
Q5. Is there any difference between “=
=” and “= = =” in behavioral modeling of verilog?
Q6. What is the use of non-blocking
assignment in behavioral modeling of verilog? How is
it different from blocking-assignment?
Q7. Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
Q8. Is there any problem in the
following code: (a) For simulations (b) For synthesis
and for post synthesis.
always @(cntrl,a,b)
begin
if(cntrl)
a <= b;
Q9. Implement following logic's using minimum number of D Flip-Flops:
a)
Clock Divide by 2
b) Clock Divide by 4
Q10. What is the difference between a Mealy and a Moore finite state machine?
Q11. Write a Verilog code to swap contents of two
registers a and b without any temporary register?
Q12. Write a Verilog code for a flip-flop and latch?
Q13. Write a Verilog code to detect a pattern 10110 from an input stream of bits.
Q14. What is the difference between reg and wire?
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