I am writing this post from my interview experiences.
1.What is setup and hold time?
2.What is latchup effect in cmos?
3.Define Electromigration in vlsi.
4.Explain CMOS operation.
5.Draw asic design flow and explain.
6.What is IR drop in vlsi?
7.Define dynamic power in cmos.
8.Draw frequency divide by two circuit.
9.How to solve setup and hold violation.
10.What is clock skew?
11.What are types of routing?
12.Explain PD flow.
13.what is LVT HVT SVT cells?
14.Write verilog code for counter?
15.What is blocking and non blocking assignments in verilog. Explain with code.
16.Difference between $monitor and $display.
17.How to resolve latch-up effect in cmos.
18.Explain clock gating technique.
19.What is metastability?
20.What is slack?
21.What is cross talk? How it affects timing.
22.How will you solve the congestion when utilization and cell density is more?
23.What is antenna effect?
25.What is cell delay and net delay?
26.How delays vary with different PVT conditions? Show the graph.
27.what is OCV?
28.what is LVS what information is obtained from LVS?
29.what is DRC?
30.What is utilization factor and Area?
31.what is difference between AOCV and POCV?
32.What is short circuit current, and how will you overcome this problem?
33.How can you reduce dynamic power?
32.Explain RTL to gds2 flow?
33.Tell me about your project experience?
34.Latch vs flip flop.
35.what is false path?
36.What are the input files required to run STA?
37.Explain sizing of the inverter?
38.What is Charge Sharing?
39.What is Body Effect?
40.Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
41.Explain important Design techniques you would follow when doing a Layout for Digital Circuits?
42.Difference between mealy and moore state machine?
43.Explain operation of 6T SRAM.
44.Write verilog code for FIFO memory.
45.Difference between task and function?
46.Write a Verilog code for synchronous and asynchronous reset?
47.What is Noise Margin? Explain the procedure to determine Noise Margin.
48.What is cell delay and net delay?
49.What is wire load model?
50.What is signal integrity? How it affects Timing?
Thank You
1.What is setup and hold time?
2.What is latchup effect in cmos?
3.Define Electromigration in vlsi.
4.Explain CMOS operation.
5.Draw asic design flow and explain.
6.What is IR drop in vlsi?
7.Define dynamic power in cmos.
8.Draw frequency divide by two circuit.
9.How to solve setup and hold violation.
10.What is clock skew?
11.What are types of routing?
12.Explain PD flow.
13.what is LVT HVT SVT cells?
14.Write verilog code for counter?
15.What is blocking and non blocking assignments in verilog. Explain with code.
16.Difference between $monitor and $display.
17.How to resolve latch-up effect in cmos.
18.Explain clock gating technique.
19.What is metastability?
20.What is slack?
21.What is cross talk? How it affects timing.
22.How will you solve the congestion when utilization and cell density is more?
23.What is antenna effect?
25.What is cell delay and net delay?
26.How delays vary with different PVT conditions? Show the graph.
27.what is OCV?
28.what is LVS what information is obtained from LVS?
29.what is DRC?
30.What is utilization factor and Area?
31.what is difference between AOCV and POCV?
32.What is short circuit current, and how will you overcome this problem?
33.How can you reduce dynamic power?
32.Explain RTL to gds2 flow?
33.Tell me about your project experience?
34.Latch vs flip flop.
35.what is false path?
36.What are the input files required to run STA?
37.Explain sizing of the inverter?
38.What is Charge Sharing?
39.What is Body Effect?
40.Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
41.Explain important Design techniques you would follow when doing a Layout for Digital Circuits?
42.Difference between mealy and moore state machine?
43.Explain operation of 6T SRAM.
44.Write verilog code for FIFO memory.
45.Difference between task and function?
46.Write a Verilog code for synchronous and asynchronous reset?
47.What is Noise Margin? Explain the procedure to determine Noise Margin.
48.What is cell delay and net delay?
49.What is wire load model?
50.What is signal integrity? How it affects Timing?
Thank You
Plz share answer also if possible
ReplyDeleteyou will get answer of some questions in my posts and answer of remaining questions will be posted in my upcoming posts.
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