Clock Tree Synthesis (CTS)

Clock Tree Synthesis (CTS)

• Basic of clock tree synthesis (CTS) is to develop the interconnect that connect the system clocks to all the cells in the chip.
• Clock Tree Synthesis (CTS) is a process which make sure that the clock signals distributed uniformly to all sequential elements in the chip.
• CTS is the process of insertion of buffers or inverters along the clock paths of design in order to balance skew and minimum insertion delay.
• It is process to built a clock tree structure between the clock source to sinks pins in chip, for example H-Tree.

Goal of CTS

• To meet the clock tree targets
• Minimum skew
• Minimum insertion delay
• To meet the clock tree DRC
• Maximum transition
• Maximum capacitance
• Maximum fanout

Checklist before CTS

• Placement is completed
• Power and Ground (PG) nets should be prerouted
• Estimated congestion
• Estimated Max transition/Capacitance
• High Fanout nets

Inputs required for CTS

• Placement Database
• Target for latency and skew if specified
• Clock tree DRC's(maximum transiton, maximum capacitance, maximum fanout and max number of buffer levels).
• CTS Constraints

Output of CTS

• Database with properly build clock tree in the design

Clock Tree Exceptions

• Exclude Pin
• Float Pin
• Stop Pin
• Non-stop Pins
• Don’t Buffer Nets
• Don’t Size Cell

Implementing Clock Tree

• It is the process of insertion of buffers or inverters along the clock paths of design in order to balance skew and minimum insertion delay. 

Clock nets before CTS

Clock nets after CTS

Clock Tree Synthesis (CTS) Quality Check

• Skew
• Pulse Width
• Duty Cycle
• Latency
• Clock tree power
• Signal integrity and crosstalk

Skew

Pulse Width

Duty Cycle

Latency

• Clock latency is defined as the total time taken by the clock signal to propagates from its source to the sinks.

Clock Tree Power

• Clock is a major power consumer in your chip.
• Clock power consumption depends on switching activity or transition and wire length.

Signal Integrity and Crosstalk

• Signal integrity is the ability of an electrical signal to carry information reliably and resist the effects of high frequency electromagnetic interference from adjacent signals. Crosstalk and electromigration are signal integrity issues.
• Crosstalk is the undesirable electrical interaction between two or more adjacent nets due to capacitive cross-coupling.
• Switching of the signal in one net (aggressor) can interfere neighbouring net (victim)due to cross coupling capacitance this is called cross talk.Cross talk may lead to setup and hold violation.
• During the transition on aggressor net causes a noise bump or glitch on victim net. This noise is known as crosstalk noise.

Clock Tree Algorithms

• H tree
• X tree
• Method of mean and median
• Recursive Geometric matching algorithm
• Pi configuration

H Tree

• Minimum skew due to the symmetry of the H tree.
• It is used for top level clock distribution not for the entire clock tree.
• Blockages can spoil the symmetry of an H tree.

H Tree

X Tree

• X tree is similar to H tree but the only difference is the connections are not rectilinear in X tree.

Method of mean and median

• Recursively partition the set of terminals into two subsets of equal size.
• Connect the center of gravity of the set to the centers of gravity of the two subsets.

Recursive Geometric Matching

• Determine a minimum cost geometric matching of n sinks.
• Find a set of n/2 line segments that match n endpoints and minimize total length.
• After each matching step, a balance point is found on each matching segment to preserve zero skew to the associated sinks.
• The set of n/2 balance points then forms the input to the next matching step.

Pi configuration

• In pi configuration,the total number of buffers inserted along the clock path is multiple of previous level.

Buffering

Clock Tree Optimization(CTO)

• Gate relocation
• Gate sizing
• Buffer relocation
• Buffer sizing
• Delay insertion
• Level adjustment

Non-Default Routing(NDR)

• Non default rules are applied to reduce the cross-talk and electromigration.
• Apply non default routing (NDR) rules for clock nets.
• Non-Default Routing (NDR) rules are
• Double spacing
• Double width
• Shielding

Non-Default Routing

Effects of CTS

• Clock buffers are added.
• Congestion may increase.
• Crosstalk noise

Checklist after CTS

• Clock skew report
• Clock tree report
• Timing report
• Area report
• Power report

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Hi I’m Designer of this blog.