Placement

Placement

• Placement is the process of placing standard cells in the design.The tool determines the location of each standard cell on the die.The tool places these cells based on the  algorithms which it uses internally.
• Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design. Placement also determines the routability of design.
• Placement will be driven by different criteria like timing driven,congestion driven and power optimization.

Goals of placement

• Area,timing and power optimizations.
• The placement should be routable.
• Minimal timing DRCs.
• Minimal cell density and pin density.

Steps in Placement stage

• Pre-placement
• Coarse placement
• Legalization
• Removing existing buffer trees
• High Fan-out Net Synthesis (HFNS)
• Timing and power optimizations
• Area recovery
• Scan-chain re-ordering
• TIE cell insertions

Inputs for Placement

• Gate level netlist
• Floorplanned database
• Logical and Physical Libraries
• Design constraints

Output of Placement

• Cell placement location
• Physical Layout Information
• Timing information

Placement Stages

• Coarse Placement: During coarse placement, the placement tool will determine an approximate location for each cell according to the timing and congestion. Coarse placement is mainly performing for timing and congestion analysis.
• Legalization Placement: During legalization placement, the placement tool will move the cells to legal locations for avoiding overlap between cells.The small changes in the cell location will change the length of wire connections leads to new timing violations.These violations can be fixed by incremental optimization.

Congestion Analysis

• If the number of routing tracks available for routing are less than the required number of routing tracks then congestion will occur.
• Complete routing area in the design is divided into routing tracks.Routing tracks helps router to laid down the metal and via shapes in the design.
• Routing area is divided into Global routing cells(GRC) to analyze the congestion.Each GRC may contain many tracks.

Reasons for congestion

• Placement of standard cells near macros.
• High standard cell density in small area.
• High pin density at edge of macros.
• Bad aspect ratio.
• Bad macro placement.

Congestion Reduction Techniques

• Macro Padding:Macro padding or halos around the macros are placement blockages around the edge of the macros. It makes sure that no standard cells are placed near the pins outs of the macros, thereby giving extra space for the macro pin connections to standard cells.
• Placement Blockages
• Cell Padding
• Using proper partial placement blockages.

High Fanout Net Synthesis (HFNS)

• High Fanout Net Synthesis (HFNS) is the process of buffering the high fanout nets to balance the load.
• High Fanout Net is the net which drives more number of loads.We set limit for maximum number of loads per net using the command set_max_fanout. The nets which more than these limit are known as High Fanout Nets.
• Clock nets, reset, scan enable nets are generally considered as High Fanout Nets.

Why High Fanout Net Synthesis (HFNS)?

• To balance the load HFNS is performed.Too many loads will affect delay number and transition times because load is directly proportional to the delay.By buffering the High Fanout Net (HFN) load can be balanced.

Where High Fanout Net Synthesis (HFNS)?

• HFNS is performed at the placement stage.
• HFNS is not performed on clock nets and don't touch attribute nets.

Scan Chain Re-ordering

What is Scan Chain?

• Scan chains are groups of flip flops that are serially connected through SI/SO pins.
• Scan chain paths are active only during test mode.
• Scan chain is a technique used in design for testing(DFT).
• Scan_in and scan_out define the input and output of a scan chain.
• Clock signal which is used for controlling all the flip flops in the scan chain during shift phase and the capture phase.

SCAN CHAINS

Why Scan Chain Re-ordering done in PnR?

• Scan chain re-ordering is the process of reconnecting the scan chains in a design to optimize the routing by re-ordering the scan chain connection which improves congestion as well as timing.
• Without re-ordering of chains,scan chains contribute to a long total wire length.
• During placement the optimization may take the scan chain difficult to route due to congestion. Hence the pnr tool will re-order the scan chain to reduce congestion and total wire length.

Before SCAN Chain Reordering

After SCAN Chain Reordering

TIE Cells

• In netlist some unused inputs are tied to either VDD/VSS. It is not recommended to connect a gate directly to the power network, so you can use TIEH or TIELO cells.

How to qualify placement

• Check legalization
• Check PG connections of all the cells
• Check congestion, place density and pin density maps
• Check for timing violations
• Check whether all don't touch cells and nets are preserved.

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vlsi4freshers

Hi I’m Designer of this blog.