Why timing analysis is important?
- Timing analysis is important because designing the chip is not enough we need to know how fast the chip is going to run and how fast the input reaches the output.We want to verify our design meet all its design constraints: area,power and timing.
Types of timing analysis
There are two types of timing analysis
- Static timing analysis:Static timing analysis is a method of verifying the timing performance of a design by checking all possible paths for timing violations without any input or output vectors.
- Dynamic timing analysis:Dynamic timing analysis is a method of verifying the timing performance of a design by applying the input vectors.
Static Timing Analysis (STA) Vs Dynamic Timing Analysis (DTA)
Static Timing Analysis (STA)
- Static Timing analysis(STA) checks every path in the design for timing violations without checking the functionality of the design.
- It is faster than dynamic timing analysis.
- Less accurate.
- Checks only the synchronous part of a design not for asynchronous part of design.
Dynamic Timing Analysis (DTA)
- Dynamic timing analysis is a method of verifying the timing performance of a design by applying the input vectors.
- Slow as compare to STA.
- very accurate.
- Checks synchronous part as well as asynchronous part of a design.
- Checks for both timing as well as functionality of design.
Some basic definitions related to timing analysis:
Clock
- Clock is a signal that oscillates between a high and a low logic.Clock controls timing in the design There can be multiple clocks in design.
Setup time
- Setup time is the minimum amount of time the data signal should be stable before the clock event so that the data are reliably sampled by the clock.
- Setup time is also defined as that input data is available and stable before clock pulse is applied.
- This applies to synchronous circuits.
Hold time
- Hold time is the minimum amount of time the data signal should be stable after the clock event so that the data are reliably sampled.
- Hold time is also defined as that input data is held stable after clock pulse is applied.
Slack
- Slack is the difference between the required time and the arrival time of a signal.
- Setup slack = Required time - Arrival time
- Hold slack = Arrival time - Required time
Clock Jitter
- Clock jitter is the variations in clock period.
- Sources of Jitter: Internal circuitry of the phase-locked loop (PLL).
Recovery and Removal time
- Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.
- Removal time is the minimum amount of time between an active clock edge and the release of an asynchronous control signal.
Timing Exceptions
Timing Exceptions are nothing but constraints which do not follow the default when doing the timing analysis. The different types of timing exceptions are
False Path
- If any path does not affect the output and does not contribute to the delay of the circuit then that path is called false path.
Multicycle Path
- Multicycle paths are the paths that require more than one clock cycle.
Max/Min Path
- This path must match a delay constraint that matches a specific value. It is not an integer like the multicycle path. For example:Delay from one point to another max: 1.76ns; min: 1.89ns.
Timing Paths
- Data path
- Clock path
- Clock gating path
- Asynchronous path
Each timing path has start and end points.
- Start points: input port of design,clock pin of flip flop.
- End points: output port of design,a clock,data input port of flip flops/latch.
Data paths
- Input ports/pin to Register(flip flop)
- Register(flip flop) to Register(flip flop)
- Register(flip flop) to Output Pin/Port
- Input ports/pin to Output Pin/Port.
Clock Path
- In the figure it is very clear that for clock path the starts from the input port of the design which is specific for the Clock input and the end point is the clock pin of a sequential element.
- In between the Start point and the end point there may be lots of Buffers or Inverters.
Clock Gating Path
- Clock path passed through gated element to achieve additional advantage ,this type of clock path is called as clock gating path.
- Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation.
Asynchronous Path
- A path from an input port to an asynchronous set or clear pin of a sequential element.
- We know that the functionality of set/reset pin is independent from the clock.
- Its level triggered pins and can start functioning at any time of data.
- We can say that this path is not in synchronous with the rest of the circuit and so such type of path is called Asynchronous path.
More STA related article published soon...
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