1.To remove the body effect, the substrate of
an n-channel enhancement mode MOSFET should be
a)Connected to the most positive bias
b)Connected to the most negative bias
c)Grounded
d)Floating
Answer: option b
2.The threshold voltage of an enhancement mode MOSFET is always.
a)Negative
b)Pbositive
c)Can be both negative as well as positive
d)indeterministics
Answer: option c
3.Assuming that the bulk NMOS device has equal source and drain doping then the effective
channel length (Leff) is related to drawn length (Ldrawn) and diffusion length (LD).
a)Leff = Ldrawn – 2 LD
b)Leff = Ldrawn – LD
c)Leff = 2Ldrawn – LD
d)None of these
Answer: option a
4.A static CMOS Inverter is powered by a supply voltage of VDD. Assuming the pull-up and
pull-down networks are equal and symmetric, which of the following statement are true.
a)The switching threshold is 2VDD
b)The switching threshold is VDD
c)The switching threshold is 4VDD
d)The switching threshold is VDD/2
Answer: option d
5.For a static CMOS, the output is high, then the state of the NMOS and PMOS are as
follows.
a)NMOS on and PMOS non-linear
b)NMOS off and PMOS non-linear
c)NMOS off and PMOS linear
d)NMOS on and PMOS linear
Answer: option c
6.For a 4 block inverter chain if the output load capacitance is
three times the minimum input capacitance of the input inverter, then
the electrical effort is.
a)2
b)4/3
c)5/3
d)3
Answer: option d
7.For an ideal CMOS inverter operating at a supply of
VDD the short circuit power dissipation is maximum at.
a)Vdd
b)Vdd/2
c)Vdd/4
d) 2Vdd
Answer: option b
8.For an ideal CMOS inverter, if the power supply VDD is
reduced to VDD/2, then everything else remaining the same,
the dynamic power dissipation of the inverter will be.
a)Increase by two
b)Increase by four
c)Decrease by eight
d)Decrease by four
Answer: option d
9.For an RC switch model, with the on –resistance of each device as R and the
intermediate load capacitance is C, the delay is then defined as.
a)0.69 RC
b)0.69 (R/2)C
c)1.38 RC
d)None of the above
Answer: option a
10.For a static CMOS circuit, there are 2, zero to one
transitions for every 4 clock cycles. The value of the activity
factor is.
a)0.5
b)2
c)1
d)0.75
Answer: option a
11.Assuming λn = λp, the gain of a MOS transistor at the
transition level is.
a)0
b)1
c)-1
d) Infinity
Answer: option d
12.For a 2-input NOR logic, the transition probability for zero to one transition
assuming equal probability of 0 and 1 is given as.
a)3/16
b)4/16
c)5/16
d) 5/32
Answer: option a
13.For a NMOS (threshold voltage = Vtn) based pass transistor based AND logic,
when both the gates are on, then for an input equal to 1 (equivalent to VDD) , the output
is.
a)VDD + 2Vtn
b)VDD - 2Vtn
c)VDD + Vtn
d)None of the above
Answer: option b
14.For a NAND-2 logic, if the widths of the pull down NMOS transistors are
doubled, then assuming no change in the load capacitance, the high-to-low propagation
delay (tpHL) for input vector (1,1) is.
a)Reduced by eight
b)Reduced by four
c)Reduced by two
d)Unchanged
Answer: option c
15.For a ratioed logic, the pull up device is.
a)Depletion Mode NMOSFET
b)Single, normally on load
c)Normally OFF Loads
d)Multiple loads
Answer: option a
16.Transmission Gate is a good transmitter of.
a)0
b)1
c)Both 0 and 1
d)None 0 and 1
Answer: option c
17.For an n-input dynamic logic the number of gates for full functionality is given
as.
a)n
b)n+1
c)2n
d) n+2
Answer: option d
18.For a static CMOS inverter, when the aspect ratio of the pull down network is increased,
then which of the following statement is true.
a)NMH increases
b)NML increases
c)TpHLincreases
d)TpLHincreases
Answer: option b
19.For a pseudo NMOS logic working such that pull up PMOS is connected supply voltage of
VDD and the pull down network is connected to ground. In such a scenario, the value of the nominal
pull down voltage is.
a)Just larger than zero volt
b)0
c)1
d)None of the above
Answer: option a
20.The static power dissipation of an ideal N-gate dynamic logic is.
a)0 Watt
b)N Watt
c)2N Watt
d)1 Watt
Answer: option a
21.In a level restoration circuit, with increasing width of the restoring transistor,
for the input going from low to high, the output voltage.
a)No Change
b)Goes LOW
c)Goes HIGH
d)None of the above
Answer: option c
22.Assuming Wn and Wp to be widths of the NMOS and PMOS transistors
of a Domino CMOS Logic, the value of tPHL (high-to-low propagation delay) is
equal to.
a)Wp/Wn
b)0
c)Wn+Wp
d)Wn/Wp
Answer: option b
23.If the output and the input capacitance of logic is Cout and Cin
respectively then the value of electrical effort is.
a)2Cout /Cin
b)Cout /Cin
c)Cin /Cout
d)None of the above
Answer: option b
23.Memories based on positive feedback falls under the class of.
a)Bistable Circuits
b)Dynamic Circuits
c)Astable Circuits
d)Multivibrators
Answer: option d
24.The time before the rising/falling clock edge till which the data should be stable for proper sampling of the data is referred to as.
a)Hold Time
b)Set-up Time
c)Clock Period
d)None of the above
Answer: option b
25.The frequency of an N stage ring oscillator with the following
parameters: Logical effort = Branching Effort = Electrical Effort = parasitic delay =
1 units and delay = 3 units is.
a)4N
b)6N
c)1/6N
d)None of the above
Answer: option c
26.Find the value of the logical effort of a NOR-2 gate whose delay is
equivalent to a CMOS inverter whose Wp/Wn = 3/1, where Wp and Wn are the
widths of the PMOS and NMOS respectively.
a)7/3
b)5/3
c)7/4
d)11/5
Answer: option c
27.The primary advantage of a Sense Amplifier Based Register.
a)Low Hold Time
b)Rail-to-rail output swing
c)Low Delay
d)Low Setup Time
Answer: option b
28.If two clock maintain a constant phase difference and have exactly the same frequency,
they are referred to as.
a)Synchronous Clocks
b)Asynchronous Clocks
c)Mesochronous Clocks
d)None of the above
Answer: option a
29.Using dual edge triggered latch, the frequency of operation is.
a)One-fourth
b)Quadrupled
c)Halved
d)None of the above
Answer: option c
30.Cascading negative and positive latches will result in a.
a)One Shot generators
b)Level Register
c)Dynamic configuration
d)Master-Slave configuration
Answer: option d
31.In which of the following logic style the CLK-CLK (bar) clocking
is insensitive to overlap.
a)Pipeline
b)C2MOS
c)NORA
d)None of the above
Answer: option b
32.The minimum clock period required to operate a sequential circuit reliably reduces with.
a)Increasing Combinational Logic Block Delay
b)Increasing Clock Skew
c)Independent of Clock Skew
d)Decreasing Clock skew
Answer: option b
33.For a latch based clocking how many phase clock sequence is required.
a)Four Phase
b)Single Phase
c)Two Phase
d)Three Phase
Answer: option c
34.For a C2MOS pipelined circuit to be race free the essential condition is.
a)All the logic function implanted should be non-inverting
b)All the logic function implanted should be inverting
c)Power fluctuation to be minimized
d)The clock should be jitter and skew free
Answer: option a
35.For a CMOS gate, the rise time at the output will depend on.
a)The effective resistance of the pull up network
b)The effective resistance of the pull down network
c)The total capacitive load the output is driving
d)All of the above
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