1.Which of the following data-types is new in System Verilog?
a)Integer
b)Logic
c)Time
d)None of the above
Answer: option b
2.bit is an unsigned data-type.But, it has 4 states.
a)True
b)False
3.Mod port is used to
a)declare the directions of signals
b)to synchronize the signal
c)make interface complex
d)None of the above
Answer: option a
3.Which of the following is false?
a)module can contain class
b)program can contain package
c)program can contain class
d)interface can contain module instance
Answer: option d
4.Which of the following is overlapping operator in assertions?
a)|->
b)|=>
c)=
d)None of the above
Answer: option a
5.In following code what happens to threads A() and B() if C() finishes first?
fork
A();
B();
C();
join_any
a)A() and B() will be killed once join-any exits after C() is completed
b)A() and B() will still run parallel to sequential code following join-any
c)join_any will block further execution until A() and B() also finishes
d)None of the above
Answer: option b
6.What is the difference between creating an object using new() and create() methods?
7.What is the difference between a bit and logic data type?8.What is the difference between logic[7:0] and byte variable in System Verilog?
9.What is the difference between a struct and union in System Verilog?
10.What is the difference between a packed array and an unpacked array?
11.What is the concept of forward declaration of a class in System Verilog?
12.Are System Verilog class members public or private by default?
13.What are interfaces in System Verilog?
14.What is a modport construct in an interface?
15.Are interfaces synthesizable?
16.What is a unique constraint in System Verilog?
17.What is the use of wait fork and disable fork constructs?
18.What is the difference between hard and soft constraints?
19.Which keyword in System Verilog is used to define Abstract classes?
20.What is difference between bounded and unbounded mailboxes? How can we create unbounded mailboxes?
21.What is an event in System Verilog? How do we trigger an event in SystemVerilog?
22.What is the difference between directed testing and constrained random verification? What are the advantages and disadvantage of both?
23.What is the difference between a sequence and sequence item?
24.What is the difference between copy(), clone(), and create() method in a component class?
25.What all different components can a UVM agent have?
26.What steps are needed to run a sequence?
27.Why should we register a class with factory?
28.What are the different phases of a UVM component?
29.What is Formal Verification?
30.What are the different methods for performing Formal Verification?
31.What is the difference between code coverage and functional coverage?
32.What are coverpoints and bins?
33.What is cross coverage?
34.What is an assertion and what are the benefits of using assertions in Verification?
35.What are different types of assertions?
36.What are the differences between Immediate and Concurrent assertions?
37.What is an implication operator?
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