1.If a net has no driver, it gets the value.
a)0
b)X
c)Z
d)None of the above
2.Which logic level is not supported by verilog?
a)U
b)X
c)Z
d)None of the above
3.Which level of abstraction level is available in Verilog but not in VHDL?
a)Behavioral level
b)Gate level
c)Dataflow level
d)Switch level
4.Default value of reg is
a)X
b)Z
c)0
d)None of the above
5.If A= 4`b011 and B= 4b`0011, then the result of A**B will be.
a)9
b)6
c)27
d)None of the above
6.If A= 4b`001x and B= 4b`1011, then result of A+B will be.
a)110X
b)1100
c)XXXX
d)None of the above
7.If A= 4`1xxz and B= 4`b1xxx, then A= = =B will return.
a)1
b)X
c)Z
d)0
8.Initial value of a=1 and b=2, then what will be final value if,
always @ (posedge clock)
a<=b;
always @ (posedge clock)
b<=a;
a)a=2,b=1
b)a=1,b=2
c)Both a and b will have same value either 0 or 1
d)None of the above
9.Variable and signal which will be updated first?
a)Variable
b)Signal
c)Can't say
d)None of the above
10.How many flops will be synthesized by the given code?
always @ (posedge clock) begin
q1<=d;
q2<=q1;
q3<=q2;
end
a)1
b)2
c)3
d)None of the above
11.Which operators has highest precedence in verilog?
a)Unary
b)Multiplication
c)Addition
d)Conditional
12.What will be the value of c in following case (after 5 sim units)?
initial begin
a=0; b=1;
c = #5 a+b;
end
a)0
b)1
c)2
d)None of the above
13.What is equivalent hardware to meet the following behavior?
always@(a)
if(a==1'b1)
output =1;
else
output=0;
a)Mux
b)Flipflop
c)Latch
d)None of the above
14.Which of the following statement are correct?
a)UDPs can have only one output
b)UDPs can have 1 to 10 inputs
c)The Z logic value is not supported
15.The task $stop is provided to
a)End simulation
b)Suspend simulation
c)Exit simulator
d)None of the above
16.Turn off delays means,gate output transition to
a)0
b)1
c)X
d)Z
17.If there is mismatch in connecting wire such as
W1[7:0]=W2[15:0]
a)The end result is W1[7:0]=W2[15:0]
b)The end result is W1[7:0]=W2[7:0]
c)The end result is W1[15:0]=W2[7:0]
d)None of the above
18.Given the following Verilog code, what value of "a" is displayed?
always @ (clk)
begin
a = 0;
a <= 1;
$display(a);
end
a)0
b)1
c)Both a and b
d)None of the above
19.The LHS of procedural continuous assignments can be
a)Registers or concatenations of registers
b)Nets or concatenation of nets
c)Arrays of nets
d)None of the above
20.For the segment is given below choose the correct answers
bufif0 #(5,6,7) c1(out,in,cntrl)
a)5=rise 6=turnoff 7=fall
b)5=fall 6=rise 7=turnoff
c)5=rise 6=fall 7=turnoff
d)5=turnoff 6=rise 7=fall
21.Which procedural assignments should be used to model a perfect combinational logic buffer?
a)always@(In)
# 5 output<=In;
b)always@(In)
output= #5 In;
c)always@(In)
# 5 output=In;
d)always@(In)
output<= #5 In;
22.Which of the following statement is incorrect?
a)Tasks are part of functions
b)Functions are part of tasks
c)Function are always synthesizable
d)Functions have some inputs
23.Which is legal negative number?
a)4'd-3
b)6'-d3
c)-6'd3
d)None of the above
24.In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list?
a)No
b)Yes
c)It depends on the coding style
d)None of the above
25.Which is not a correct method of specifying time scale in verilog?
a)1ns/1ps
b)10ns/1ps
c)100ns/100ps
d)100ns/110ps
Answers: 1.c 2.a 3.d 4.a 5.c 6.c 7.d 8.a 9.b 10.c 11.a 12.b 13.a 14.d 15.b 16.d 17.b 18.a 19.a 20.c 21.c 22.a 23.c 24.b 25.d
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Click here for part 3
https://www.vlsi4freshers.com/2020/07/verilog-interview-questions-part-3.html
Answer for quize 2
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DeleteHi Sir/Mam,
ReplyDeleteFirstly I would like to thanks for giving this questions , but what I found that it was very basic level .
Please upload some more tough question which are really asked in interviews.
Ok
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