1. The total number of multiple stuck-at faults possible in a 3-input NAND gate is.
a) 27
b) 81
c) 80
d) None of the above
Solution: Number of multiple stuck-at faults = 3^4-1=80
2. The total number of possible single stuck-at faults in the below circuit will be.
a) 14
b) 21
c) 7
d) None of the above
Answer: a
3. The total number of input vectors that can detect the fault C stuck-at-0 is.
a) 3
b) 4
c) 5
d) None of the above
Answer: a
4. The number of test vectors to detect all single stuck-at faults in a 3-input NAND gate is.
a) 3
b) 4
c) 5
d) None of the above
Solution: Number of test vectors = 4 and test pattern are {011,101,110,111}.
5. For a gate level netlist with 3 lines, the number of single and
multiple stuck-at faults are.
a) 6 and 27
b) 6 and 26
c) 12 and 26
d) None of the above
Solution: Number of single stuck-at faults = 2 x 3 =6
Number of multiple stuck-at faults = 3^3 – 1 = 26
6. For which of the following test strategies, we can carry out testing at the rated clock frequency of the chip?
a) Scan based testing
b) Built-in self-test
c) Exhaustive testing
d) None of the above
Answer: b
7. For a 32-bit LFSR compacting a 10,000-bit serial bit pattern, the probability of aliasing is approximately given by.
a) 1 / 2^32
b) 32 / 10000
c) 1 / 2^10000
d) None of the above
Answer: a
a) The test generation problem is reduced to that for a combinational circuit
b) Special shift register test sequences are applied to test faults in the scan flip-flops.
c) The fanout of a scan flip-flop is greater than that of a normal flip-flop in the original non-scan version of the circuit.
d) All of the above
Answer: d
9. Suppose we are carrying out parallel fault simulation with 50 test vectors on a circuit with 100 faults. How many passes of simulation will be required (without fault dropping) on a machine with word size of 32 bits?
a) 5000
b) 200
c) 157
d) None of the above
Answer: b
10. Which of the following are true with respect to testing and verification?
d) None of the above
Answer: b
10. Which of the following are true with respect to testing and verification?
a) Verification is done once while testing is done separately for every manufactured device
b)Verification ensures quality of the design,while testing ensures quality of the manufactured devices
c) Verification precedes testing in the design cycle.
d) All of the above
Answer: d
11. For a 3-input NAND gate, which of the following set of faults are equivalent?
Answer: d
11. For a 3-input NAND gate, which of the following set of faults are equivalent?
a) Input lines stuck-at-1 and output stuck-at-1
b) Input lines stuck-at-1 and output stuck-at-0
c) Input lines stuck-at-0 and output stuck-at-1
c) Input lines stuck-at-0 and output stuck-at-1
d) Input lines stuck-at-0 and output stuck-at-0
Answer: c
12. For a 3-input OR gate with inputs A, B, C and output F, which of the following are true with respect to fault dominance?
Answer: c
12. For a 3-input OR gate with inputs A, B, C and output F, which of the following are true with respect to fault dominance?
a) F/0 dominates A/0
b) F/0 dominates B/1
c) F/0 dominates C/1
d) None of the above
Answer: a
13. For a 3-input NAND gate with inputs A, B, C and output F, which of the following are true with respect to fault dominance?
Answer: a
13. For a 3-input NAND gate with inputs A, B, C and output F, which of the following are true with respect to fault dominance?
a) F/1 dominates A/1
b) F/0 dominates B/1
c) F/0 dominates C/0
d) None of the above
Answer: b
14. The number of test vectors to detect all single stuck-at faults in a 10 input XOR gate is.
Answer: b
14. The number of test vectors to detect all single stuck-at faults in a 10 input XOR gate is.
a) 2
b) 22
c) 11
d) 3
Answer: d
15. The minimum number of test vectors required to detect all single stuck-at faults in a 7 input exclusive-OR gate is.
a) 5
b) 4
c) 3
d) 2
Answer: d
16. In a scan path design there are 250 scan flip-flops that are connected in a scan chain. For applying 5000 combinational test vectors, how many clock cycles will be required?
a) 1255250
b) 1000000
c) 50600
d) None of the above
Solution: The number of clock cycles required is = (ns + 1) nc + ns, where ns is number of scan flip-flops and nc is the number of combinational test vectors. Here, (250 + 1) x 5000 + 250 = 1255250.
17. Which of the following are true for detecting a stuck-open fault in a CMOS gate?
Answer: d
15. The minimum number of test vectors required to detect all single stuck-at faults in a 7 input exclusive-OR gate is.
a) 5
b) 4
c) 3
d) 2
Answer: d
16. In a scan path design there are 250 scan flip-flops that are connected in a scan chain. For applying 5000 combinational test vectors, how many clock cycles will be required?
a) 1255250
b) 1000000
c) 50600
d) None of the above
Solution: The number of clock cycles required is = (ns + 1) nc + ns, where ns is number of scan flip-flops and nc is the number of combinational test vectors. Here, (250 + 1) x 5000 + 250 = 1255250.
17. Which of the following are true for detecting a stuck-open fault in a CMOS gate?
a) A unique test pattern can detect a particular fault
b) A pair of test patterns is required to detect a fault
c) The stuck-open faults are equivalent to single stuck-at faults in the circuit
d) None of the above
Answer: b
18. Which of the following statements is false?
a) Verification guarantees the quality of the manufactured device
b) Verification guarantees the quality of the design
c) We carry out testing on all the manufactured devices
d) None of the above
Answer: a
d) None of the above
Answer: b
18. Which of the following statements is false?
a) Verification guarantees the quality of the manufactured device
b) Verification guarantees the quality of the design
c) We carry out testing on all the manufactured devices
d) None of the above
Answer: a
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