PVT is abbreviation for Process, Voltage and Temperature.
Process
Process variation is the deviation in attributes of transistor during the fabrication.During fabrication process, the area of die at the center and at the boundary will have different process variation because layers which will be getting fabricated can not be uniform all over the die,as we go away from the center of the die,layers can differ in their sizes.
Process variation is gradual.It can not be abrupt.
Process variation is different for different technologies.There are few important factors which can cause process variation.
1.Oxide thickness variation(tox)
Drain current equation
Current flowing through the channel depends on mobility and oxide capacitance(Cox) and W/L ratio.Any of these parameter change it will change the current value.In other words,it will affect the delay of the circuit.
The relation between process and delay can be better understood with the following curve shown in below figure.
From figure, we say that delay is more for slow process MOSFETs and delay is less for fast process MOSFETs.
Voltage
Supply voltage for a chip is very less. Lets say chip is operating at 5v. So there are chances that at certain instance of time this voltage may vary. It can go to 5.1v or 4.9v.
There are various reasons for voltage variation.
Global voltage variation: Noise in supply voltage say noise in output of voltage regulator to full chip can cause an overshoot and undershoot.
The other reason for supply voltage variation is IR drop. IR drop is caused by the current flow over the parasitic resistance of the power grid. IR drop reduces the supply voltage from the required value.
The voltage that any semiconductor chip works upon is given from externally.The voltage come from DC source or some voltage regulator.
Voltage regulator will not give same voltage over a period of time. It can go above or below the expected voltage and hence it will cause current to change making the circuit slower or faster than earlier.
From the above current equation it can be seen that more is voltage,more is the current and hence delays are less.
Temperature
Junction temperature of a transistor impacts transistor current.The chip is designed such that it is working in extreme global conditions. Switching of a large number of cells at the same time inside a chip creates local temperature variation in chip due to large power dissipation. This is also cause variation in junction temperature.As temperature increases random motion of carriers in channel increases due to collision effect thus degrading mobility of carriers. When temperature is less randomness decreases and due to a better mobility current increases and delay decreases.
But a behavior contrary to this was observed during low temperature in lower technology nodes especially less than 65nm onward. Instead of reduced delay a greater delay was observed.This is known as temperature inversion.
Process
Process variation is the deviation in attributes of transistor during the fabrication.During fabrication process, the area of die at the center and at the boundary will have different process variation because layers which will be getting fabricated can not be uniform all over the die,as we go away from the center of the die,layers can differ in their sizes.
Process variation is gradual.It can not be abrupt.
Process variation is different for different technologies.There are few important factors which can cause process variation.
1.Wavelength of the UV light
2.Manufacturing defects
The affects of process variation are given below.1.Oxide thickness variation(tox)
2.Transistor width(W) and length(L)
3.RC Variation
These variations will cause the parameters like threshold voltage(Vth) to change its value from expected. Threshold voltage depends on oxide thickness(tox), source to body voltage(Vsb).Drain current equation
ID = (1/2)μnCox (W/L)(VGS – VTh)2
The relation between process and delay can be better understood with the following curve shown in below figure.
From figure, we say that delay is more for slow process MOSFETs and delay is less for fast process MOSFETs.
Voltage
Supply voltage for a chip is very less. Lets say chip is operating at 5v. So there are chances that at certain instance of time this voltage may vary. It can go to 5.1v or 4.9v.
There are various reasons for voltage variation.
Global voltage variation: Noise in supply voltage say noise in output of voltage regulator to full chip can cause an overshoot and undershoot.
The other reason for supply voltage variation is IR drop. IR drop is caused by the current flow over the parasitic resistance of the power grid. IR drop reduces the supply voltage from the required value.
The voltage that any semiconductor chip works upon is given from externally.The voltage come from DC source or some voltage regulator.
Voltage regulator will not give same voltage over a period of time. It can go above or below the expected voltage and hence it will cause current to change making the circuit slower or faster than earlier.
From the above current equation it can be seen that more is voltage,more is the current and hence delays are less.
Temperature
Junction temperature of a transistor impacts transistor current.The chip is designed such that it is working in extreme global conditions. Switching of a large number of cells at the same time inside a chip creates local temperature variation in chip due to large power dissipation. This is also cause variation in junction temperature.As temperature increases random motion of carriers in channel increases due to collision effect thus degrading mobility of carriers. When temperature is less randomness decreases and due to a better mobility current increases and delay decreases.
But a behavior contrary to this was observed during low temperature in lower technology nodes especially less than 65nm onward. Instead of reduced delay a greater delay was observed.This is known as temperature inversion.
Temperature Inversion
Change in junction temperature impacts mobility and threshold voltage of a transistor.Both are inversely proportional to temperature.
As temperature increases, mobility and threshold voltage start decreasing. The delay is inversely proportional to the mobility and directly proportional to the threshold voltage
Id= (1/2)μnCox (W/L)(VGS – VTh)2
.
In the higher technology node, where the supply voltage is very high, the effect of threshold voltage Vth is very low as (Vgs – Vth) value is large. Hence mobility plays huge role in deciding drain current. So at higher technology nodes, when the temperature increases mobility decreases and as a result the delay will increase.
In the lower technology node especially less than 65nm, the supply voltage is very low, so the (Vgs – Vth) difference is small and the square of this value is very small resulting reduced drain current, which increases delay at lower temperature. Where at other end above 65nm delay decreases at lower temperature.
Timing analysis and fixing at different corners which consists of combinations of PVT for worst case delay and best case delay is done in the design to make the chip functional at all possible situation in real time.
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