1.Write verilog code for implementation of 8*1 MUX using ASSIGN statement.
Code:
module mux_q1(output Y,input [7:0]In,[2:0]S);
assign Y=In[S];
endmodule
Testbench:
module test_mux1;
reg[7:0] A;
reg [2:0] B;
wire y;
mux_q1 aa (.In(A),.S(B),.Y(y));
initial
begin
A = 8'b01111111;
B = 3'b000;
#5
A = 8'b11111110;
B = 3'b111;
#5
A = 8'b11111011;
B= 3'b101;
end
endmodule
2.Write verilog code for implementation of 8*1 MUX using IF ELSE and CASE statement.
2.Write verilog code for implementation of 8*1 MUX using IF ELSE and CASE statement.
Using If-else
module mux_q2_1(Y,In,S);
input [7:0]In;
input[2:0]S;
output reg Y;
always @(*)
begin
if(S == 3'b000)
Y = In[0];
else if(S == 3'b001)
Y = In[1];
else if(S == 3'b010)
Y = In[2];
else if(S == 3'b011)
Y = In[3];
else if(S == 3'b100)
Y = In[4];
else if(S== 3'b101)
Y = In[5];
else if(S == 3'b110)
Y = In[6];
else
Y = In[7];
end
endmodule
Testbench:
module test_mux1;
reg[7:0] A;
reg [2:0] B;
wire y;
mux_q1 aa (.In(A),.S(B),.Y(y));
initial
begin
A = 8'b01111111;
B = 3'b000;
#5
A = 8'b11111110;
B = 3'b111;
#5
A = 8'b11111011;
B= 3'b101;
end
endmodule
Using Case:
module mux_q2(Y,In,S);
input [7:0]In;
input[2:0]S;
output reg Y;
always @(*)
begin
case(S)
3'b000 : Y =In[0];
3'b001 : Y =In[1];
3'b010 : Y =In[2];
3'b011 : Y =In[3];
3'b100 : Y =In[4];
3'b101 : Y =In[5];
3'b110 : Y =In[6];
3'b111 : Y=In[7];
endcase
end
endmodule
Testbench:
module test_mux1;
reg[7:0] A;
reg [2:0] B;
wire y;
mux_q1 aa (.In(A),.S(B),.Y(y));
initial
begin
A = 8'b01111111;
B = 3'b000;
#5
A = 8'b11111110;
B = 3'b111;
#5
A = 8'b11111011;
B= 3'b101;
end
endmodule
3.Write verilog code for implementation of 2 to 4 decoder using any statement.
Code :
module decoder_q(output reg[3:0] Y,input enable,[1:0]X);
always @(*)
begin
if(enable)
begin
case(X)
2'b00:Y=4'b1000;
2'b01:Y=4'b0100;
2'b10:Y=4'b0010;
2'b11:Y=4'b0001;
default Y=0;
endcase
end
end
endmodule
Testbench:
module test_decoder;
Testbench:
module test_decoder;
wire [3:0]y;
reg en;
reg[1:0] A;
decoder_q aa(.Y(y),.enable(en),.X(A));
initial
begin
en = 1;
A = 2'b00;
#5
en = 1;
A = 2'b01;
#5
en = 1;
A = 2'b10;
#5
en = 1;
A = 2'b11;
end
endmodule
4.Write verilog code for implementation of octal to decimal binary encoder using a case statement.
Code:
module octal_binary(output reg[2:0] Y,input enable,[7:0]In);
always @(*)
begin
if(enable)
begin
case(In)
8'b10000000:Y=3'b000;
8'b01000000:Y=3'b001;
8'b00100000:Y=3'b010;
8'b00010000:Y=3'b011;
8'b00001000:Y=3'b100;
8'b00000100:Y=3'b101;
8'b00000010:Y=3'b110;
8'b00000001:Y=3'b111;
default Y=0;
endcase
end
end
endmodule
TestBench:
module test_encoder;
wire [2:0]y;
reg en;
reg[7:0] A;
octal_binary aa1(.Y(y),.enable(en),.In(A));
initial
begin
en = 1;
A = 8'b10000000;
#5
en = 1;
A = 8'b01000000;
#5
en = 1;
A = 8'b00000010;
#5
en = 1;
A = 8'b00100000;
#5
A=8'b00000100;
end
endmodule
5.Write verilog code for implementation of 8*3 priority encoder using a case statement.
Code:
module priority_en(output reg[2:0] out,input[7:0]A);
always @(*)
begin
casex(A)
8'b00000001 : out = 3'b000;
8'b0000001x : out= 3'b001;
8'b000001xx : out = 3'b010;
8'b00001xxx : out = 3'b011;
8'b0001xxxx : out = 3'b100;
8'b001xxxxx : out = 3'b101;
8'b01xxxxxx : out = 3'b110;
8'b1xxxxxxx : out = 3'b111;
default : out = 3'bxxx;
endcase
end
endmodule
Testbench:
module test_en;
wire [2:0] Y;
reg [7:0]in;
priority_en aa(.out(Y),.A(in));
initial
begin
in = 8'b01111111;
#5 in = 8'b10000101;
#5 in = 8'b00110010;
#5 in = 8'b00000001;
#5 in= 8'b01000101;
#5 in= 8'b00111111;
end
endmodule
6.Write verilog code for implementation of ALU that will perform following operation.
Code:
module ALU(output reg[15:0] out ,input [15:0]In1,In2,input[3:0]oper);
reg y;
always @(*)
begin
case(oper)
4'b0000 :{y,out}=In1+In2;
4'b0001 : {y,out} = In1-In2;
4'b0011 : begin out = In1;
out = out<<1'b1; end
4'b0100 : begin out = In1;
out = out>>1'b1;end
4'b0101 : out = In1|In2;
4'b0110 : out = In1&In2;
4'b0111 : out = 16'hFFFF-In1;
4'b1000 : out = (16'hFFFF-In1) + 1'b1;
default : out = 16'hxxxx;
endcase
end
endmodule
Testbench:
module test_alu;
reg [15:0]in1,in2;
reg [3:0]op;
wire[15:0]y;
ALU aa(.out(y),.In1(in1),.In2(in2),.oper(op));
initial
begin
in1 = 16'h0006;
in2 = 16'h0001;
#5 op = 4'b0000;
#5 op = 4'b0001;
#5 op= 4'b0011;
#5 op= 4'b0100;
#5 op= 4'b0101;
#5 op= 4'b0010;
#5 op= 4'b0110;
#5 op= 4'b0111;
#5 op= 4'b1000;
end
7.Write verilog code for implementation of T- FF by using D-FF.
Code:
D-flipflop:
module d_flipflop(output reg q,input d,clk,rst);
always @(posedge clk or negedge rst)
if(~rst)
q<=1'b0;
else
q<=d;
endmodule
T flipflop:
module t_ff(output reg Q,input clk1,rst1,T);
wire a,b;
assign b=T^a;
always @(*)
Q=a;
d_flipflop aa(.q(a),.d(b),.clk(clk1),.rst(rst1));
endmodule
Test bench:
module test_tff;
reg clk,rst;
reg t;
wire q;
t_ff aa (.Q(q),.T(t),.clk1(clk),.rst1(rst));
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
rst=0;
t = 0; #10
rst=1;
t = 1; #10
rst=1;
t=0; #5
rst=1;
t=1;
end
endmodule
8.Write verilog code for implementation of JK- FF.
Code:
module jk_ff(output reg q,input j,k,clk,rst);
always @(posedge clk,negedge rst)
begin
if(~rst)
q=0;
else if(j==0 && k==0)
q<=q;
else if(j==0 && k==1)
q<=0;
else if(j==1 && k==0)
q<=1;
else
q<=~q;
end
endmodule
Testbench:
module test_jkff;
reg clk,rst;
reg j,k;
wire q;
jk_ff aa (q,j,k,clk,rst);
initial
begin
clk=0;
forever #5 clk = ~clk;
end
initial
begin
rst=0;
#5
j=0;
k=0; #5
rst=1;
j=0;
k=1; #5
rst=1;
j=1;
k=0; #5
rst=1;
j=1;
k=1;
end
endmodule
9.Write verilog code for implementation of a 4-bit counter such that if select= 1 it will count up and if select =0 it will count down. Implement it by using flip-flop and MUX.
Code:
module up_down_counter(output reg[3:0 ]Q,input clk,rst,sel );
always @(posedge clk or posedge rst)
begin
if (rst)
Q<=4'b0000;
else if(sel)
Q<= Q + 4'b0001;
else
Q <=Q - 4'b0001;
end
endmodule
Testbench:
module test_counter;
reg clk1, rst1,S;
wire [3:0] q;
up_down_counter aa(.Q(q),.clk(clk1),.rst(rst1),.sel(S));
initial begin
clk1=0;
forever #5 clk1=~clk1;
end
initial begin
rst1=1;
S=0;
#5;
rst1=0;
S=0;
#5;
S=1;
#5;
S=0;
#5;
S=1;
end
endmodule
10.Write verilog code for implementation of the shift register(SISO) by using D-FF.
Code:
module siso(output [3:0]dout,input clk1,rst1,[3:0]din);
d_flipflop aa0(.q(dout[0]),.d(din),.clk(clk1),.rst(rst1));
d_flipflop aa1(.q(dout[1]),.d(dout[0]),.clk(clk1),.rst(rst1));
d_flipflop aa2(.q(dout[2]),.d(dout[1]),.clk(clk1),.rst(rst1));
d_flipflop aa3(.q(dout[3]),.d(dout[2]),.clk(clk1),.rst(rst1));
endmodule
D-flipflop:
module d_flipflop(output reg q,input d,clk,rst);
always @(posedge clk or negedge rst)
if(~rst)
q<=1'b0;
else
q<=d;
endmodule
Testbench:
module test_siso;
reg clk,rst;
reg[3:0]in;
wire [3:0] y;
siso aa(.dout(y),.clk1(clk),.din(in),.rst1(rst));
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
rst = 1'b0;
#5
rst = 1'b1;
in = 4'b1111;
end
endmodule
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