1. Compared to RISC processors, CISC processors contain
a) More registers and smaller instruction set
b) Larger instruction set and less registers
c) Less registers and smaller instruction set
d) More transistor elements
2. Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory?
a) Reference bit
b) Valid bit
c) Dirty bit
d) Tag bit
3. The decimal integer value of 1101 1001 (in 2’s complement form) is
a) -39
b) 24
c) -57
d) -88
4. Which of the following keeps track of instruction execution sequence?
a) Stack pointer
b) Accumulator
c) Instruction register
d) Program counter
5. A pipelined CPU has a speed up of 4.5 over non-pipelined CPU and has an efficiency of 90%. How many stages are there?
a) 6
b) 4
c) 5
d) 3
6. A 2 way set associative cache is 256 Kilo bytes in size. What is the number of sets if block size is 16 Bytes?
a) 1024
b) 4096
c) 8192
d) None of the above
7. DMA interface unit eliminates the need to use CPU registers to transfers data from
a) MAR to MBR
b) MBR to MAR
c) I/O units to memory
d) Memory to I/O units
8. Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is
a) 2.16
b) 4.16
c) 4.20
d) None of the above
9. More than one word is put in one cache block to
a) Exploit temporal locality references in a program
b) Exploit spatial locality references in a program
c) Reduce miss penalty
d) All of the above
10. How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?
a) 10^9 cycles
b) 50 x 10^7 cycles
c) 10^8 cycles
d) None of the above
11. A = 1111 1010, B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is
a) 1001 1100
b) 1010 0101
c) 1101 0101
d) 1100 0100
12. Main difference between CISC and RISC is
a) RISC has few instructions
b) RISC has few addressing modes
c) CISC is having fewer registers
d) Both a and b
13. How many separate address and data lines are needed for a memory of 8K × 16?
a) 13 address, 3 data lines
b) 12 address, 4 data lines
c) 13 address, 16 data lines
d) 13 address, 4 data lines
14. Most relevant addressing mode to write position independent code is
a) Relative
b) Direct
c) Indirect
d) Indexed Mode
15. Booth’s algorithm is used in floating point
a) Addition
b) Multiplication
c) Subtraction
d) Division
16. A two level memory system has levels with access time T1 = 15 ns and T2 = 200 ns. The hit ratio for this system is 0.9. If hit ratio is made to 1 then what will be the new value of T1?
a) 10ns
b) 20ns
c) 25ns
d) 15ns
17. A direct mapped cache is of size 64 KB with block size 32 B. Logical address generated is 32 bit. What is the bits required for tag and block field?
a) 16,16
b) 16,11
c) 21,11
d) None of the above
18. A cache uses 8-way set associative mapping. The number of blocks in the cache is 256, each of size 16 words. Main memory is 16 bit. What is the number of tag comparison required?
a) 16
b) 32
c) 8
d) 128
19. Consider a cache with 128 blocks of 16-words each. CPU generates 16 bit address. What is the tag size if 4-way Set associative mapping is used?
a) 6
b) 7
c) 8
d) 9
20. A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
a) 4
b) 6
c) 5
d) 7
21. The amount of ROM needed to implement a 4 bit multiplier is
a) 64 bits
b) 128 bits
c) 1Kbits
d) 2Kbits
22. The minimum time delay between the initiation of two independent memory operations is called.
a) Cycle time
b) Access time
c) Latency time
d) None of the above
23 Number of chips (128 x 8 RAM) needed to provide a memory capacity of 2048 bytes
a) 8
b) 16
c) 4
d) None of the above
24. The address space of 8086 CPU is
a) One Megabyte
b) 256 Kilobytes
c) 64 Kilobytes
d) None of the above
25. The cache hit ratio for this initialization loop is
a) 0%
b) 25%
c) 50%
d) 75%
Answers: 1. b 2. c 3. a 4.d 5. c 6. c 7. d 8. b 9. b 10. b 11. d 12. d 13. c 14. a 15. b 16. d 17. b 18. c 19. b 20.c 21. d 22. a 23. b 24. a 25. c
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