There are many reasons why the noise plays an important role in the deep sub-micron technologies:
1. Increasing number of metal layers
2. Vertically dominant metal aspect ratio
3. Higher routing density due to finer geometry
4. Lower supply voltage
5. Faster wave forms due to higher frequencies
Crosstalk
Crosstalk is the undesirable electrical interaction between two or more adjacent nets due to capacitive cross-coupling.
Switching of the signal in one net (aggressor) can interfere neighbouring net (victim)due to cross coupling capacitance this is called cross talk.
Switching of the signal in one net (aggressor) can interfere neighbouring net (victim)due to cross coupling capacitance this is called cross talk.
Aggressor is a net which creates impact on the other net. Victim is a net which is impacted by aggressor net.
Crosstalk has two effects.
1. Crosstalk Noise: During the transition on aggressor net causes a noise bump or glitch on victim net. This noise is known as crosstalk noise.In deep submicron technologies noise plays an important role in terms of functionality or timing of device.
2. Crosstalk Delay: It implies the delay happening in the output transition of victim due to transition of aggressor. Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of victim net.
Crosstalk Glitch Analysis
2. Crosstalk Delay: It implies the delay happening in the output transition of victim due to transition of aggressor. Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of victim net.
Crosstalk Glitch Analysis
A steady signal net can have a positive glitch or negative glitch due to charge transferred by the switching aggressors through the coupling capacitance.
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| Glitch due to aggressor |
In the above figure, the NAND cell switches and charges its output net (labeled Aggressor). Some of the charge is also transferred to the victim net through the coupling capacitance Cc and results in the positive glitch.
The amount of charge transferred is directly related to the coupling capacitance Cc between the aggressor and the victim net. The charge transferred on the grounded capacitance's of the victim net causes the glitch. The steady value on the victim net (in this case, 0 or low) is restored because the transferred charge is dissipated through the pull-down stage of the driving cell INVERTER.
The magnitude of the glitch caused is depends upon a various factors.Some of these factors are given below.
1. Coupling capacitance between the aggressor net and victim: If coupling capacitance Cc is greater ,the magnitude of the glitch is larger.
2. Slew of the aggressor net: The faster the slew at the aggressor net, the larger the magnitude of glitch. In general, faster slew is because of higher output drive strength for the cell driving the aggressor net.
3. Victim net grounded capacitance: The smaller the grounded capacitance on the victim net, the magnitude of the glitch is larger.
4. Victim net driving strength: The smaller the output drive strength of the cell driving the victim net, the magnitude of the glitch is larger.
Glitch is very critical for the sequential cells example:flip-flops, latches and memories, where a glitch on the clock or asynchronous set/reset can be catastrophic to the functionality of the design.
Glitch magnitude may be large enough to be seen as a different logic value by the fanout cells for example a victim at logic 0(LOW) may appear as logic 1(HIGH) for the fanout cells.
Types of Glitches:
Rise and Fall Glitches: Rise or positive glitch induced by crosstalk from a rising aggressor net on a victim net which is steady low. Fall glitch induced by crosstalk from a falling aggressor net on a victim net which is steady high.
Overshoot and Undershoot Glitches: When a rising aggressor couples to a steady high victim net causes an Overshoot glitch. When a falling aggressor couples to a steady low victim net causes an Undershoot glitch.
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| Types of Glitches |
The glitch calculation is based upon the amount of current injected by the switching aggressor and the RC interconnect for the victim net, and the output impedance of the cell driving the victim net. The detailed glitch calculation is based upon the library models.
Glitch caused by coupling from a switching aggressor can propagate through the fanout cell depending upon the fanout cell and glitch attributes such as glitch height and glitch width. This analysis can be based on DC or AC noise thresholds. The DC noise margin only check the glitch magnitude and the AC noise margin check other attributes such as glitch width and fanout cell output load.
DC Noise Margin
The DC noise margin is a check used for glitch magnitude and refers to the DC noise limits on the input of a cell while ensuring proper logic functionality.
For example, the output of an inverter cell may be high as long as the input stays below the maximum value of VIL. The output of the inverter cell may be low as long as the input stays above the minimum value of VIH.
VOH is the range of output voltage that is considered as a logic 1 or high. VOL is the range of output voltage that is considered as a logic 0. VIL is the range of input voltage that is considered a logic 0 or low. VIH is the range of input voltage that is considered as a logic 1.
AC Noise Margin
In many cases a design may not pass the conservative DC noise analysis limits. So,it is important to verify the impact of glitches with respect to the glitch width and the output load of the cell.
The AC noise region depends upon the output load and the glitch width.
To conclude different inputs of the cell have different limits on the glitch threshold which is a function of the glitch width and output capacitance. These limits are separate for input high (low transition glitch) and for input low (high transition glitch). The noise analysis check the height as well as the width of the glitch and analyzes whether glitch can be neglected or whether glitch can propagate to fanouts.
What happens when there are multiple aggressors
When multiple nets switch concurrently the crosstalk coupling noise effect on the victim is added due to multiple aggressors.
To find the bump height on victim net due to all aggressor A1,A2,A3 and A4 is to add all bump height.
Above is a example when all aggressors switch concurrently.But it is very unlikely.
Lets take a example when all aggressor do not switch concurrently.
Timing Window concept:
Lets check the glitch impact with multiple aggressor replace the waveforms with timing windows.
For crosstalk glitch due to multiple aggressors, the analysis must include the timing correlation of the aggressor nets and determine whether the multiple aggressors can switch concurrently.Timing analysis obtains this information from the timing windows of the aggressor nets.
Based on whether the multiple aggressors can switch concurrently, the glitches due to individual aggressors are combined for the victim net.
Crosstalk Delay Analysis
It implies the delay happening in the output transition of victim due to transition of aggressor. Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of victim net.
Positive and Negative Crosstalk
Positive crosstalk: The aggressor net has rising transition at the same time when the victim net has a falling transition. The aggressor net switching in opposite direction increase delay for victim.The positive crosstalk impacts the driving cell as well as the net interconnect the delay for both gets increased because charge required for the coupling capacitance is more.
Glitch caused by coupling from a switching aggressor can propagate through the fanout cell depending upon the fanout cell and glitch attributes such as glitch height and glitch width. This analysis can be based on DC or AC noise thresholds. The DC noise margin only check the glitch magnitude and the AC noise margin check other attributes such as glitch width and fanout cell output load.
DC Noise Margin
The DC noise margin is a check used for glitch magnitude and refers to the DC noise limits on the input of a cell while ensuring proper logic functionality.
For example, the output of an inverter cell may be high as long as the input stays below the maximum value of VIL. The output of the inverter cell may be low as long as the input stays above the minimum value of VIH.
VOH is the range of output voltage that is considered as a logic 1 or high. VOL is the range of output voltage that is considered as a logic 0. VIL is the range of input voltage that is considered a logic 0 or low. VIH is the range of input voltage that is considered as a logic 1.
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| DC Characteristics of Inverter Cell |
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| Glitch check on basis of DC noise margin |
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| DC Noise Margin |
In many cases a design may not pass the conservative DC noise analysis limits. So,it is important to verify the impact of glitches with respect to the glitch width and the output load of the cell.
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| AC noise rejection region |
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| Load determines size of propagated glitch |
To conclude different inputs of the cell have different limits on the glitch threshold which is a function of the glitch width and output capacitance. These limits are separate for input high (low transition glitch) and for input low (high transition glitch). The noise analysis check the height as well as the width of the glitch and analyzes whether glitch can be neglected or whether glitch can propagate to fanouts.
What happens when there are multiple aggressors
When multiple nets switch concurrently the crosstalk coupling noise effect on the victim is added due to multiple aggressors.
To find the bump height on victim net due to all aggressor A1,A2,A3 and A4 is to add all bump height.
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| When all aggressors switch concurrently |
Above is a example when all aggressors switch concurrently.But it is very unlikely.
Lets take a example when all aggressor do not switch concurrently.
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| Bump height due to A1 aggressor |
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| Bump height due to A2 aggressor |
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| Bump height due to A3 aggressor |
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| Bump height due to A4 aggressor |
Lets check the glitch impact with multiple aggressor replace the waveforms with timing windows.
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| Timing Window |
Based on whether the multiple aggressors can switch concurrently, the glitches due to individual aggressors are combined for the victim net.
Crosstalk Delay Analysis
It implies the delay happening in the output transition of victim due to transition of aggressor. Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of victim net.
Positive and Negative Crosstalk
Positive crosstalk: The aggressor net has rising transition at the same time when the victim net has a falling transition. The aggressor net switching in opposite direction increase delay for victim.The positive crosstalk impacts the driving cell as well as the net interconnect the delay for both gets increased because charge required for the coupling capacitance is more.
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| Positive Crosstalk Delay |
Negative crosstalk: The aggressor net is rising transition at the same time as the victim net. The aggressor net switching in same direction decrease delay of the victim. The negative crosstalk impacts the driving cell as well as the net interconnect - the delay for both gets decreased because charge required for the coupling capacitance is less.
Crosstalk impact on timing analysis:
Setup Analysis
Data path sees positive crosstalk delay so that it takes longer for the data to reach the destination.
Capture clock path sees negative crosstalk delay so that the data is captured by the capture flip-flop early.
Hold Analysis
4.Fast slew rate: A fast slew rate on the net implies that it is less susceptible to crosstalk and is inherently immune to crosstalk effects.
5.Increased the drive strength of victim net.
6.Decrease the drive strength of aggressor net.
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| Negative Crosstalk Delay |
Crosstalk impact on timing analysis:
Setup Analysis
The static timing analysis with crosstalk analysis verifies the design with the worst case crosstalk delays for the data path and the clock paths.
The worst condition for setup check is
When both the launch clock path and the data path have positive crosstalk and the capture clock path has negative crosstalk.
Launch clock path sees positive crosstalk delay so that the data is launched late.Data path sees positive crosstalk delay so that it takes longer for the data to reach the destination.
Capture clock path sees negative crosstalk delay so that the data is captured by the capture flip-flop early.
Hold Analysis
The worst condition for hold check occurs when both the launch clock path and the data path have negative crosstalk and the capture clock path has positive crosstalk.
Launch clock sees negative crosstalk delay so that the data is launched early.
Data path sees negative crosstalk delay so that it reaches the destination early.
Capture clock sees positive crosstalk delay so that the data is captured by the capture flipflop late.
There is one important difference between the hold and setup analysis.The launch and capture clock edge are normally the same edge for the hold analysis.The clock edge through the common clock portion cannot have different crosstalk contributions for the launch clock path and the capture clock path. So the crosstalk impact on the common portion of the clock tree is not considered for the hold analysis.The positive crosstalk contribution of the launch clock and negative crosstalk contribution of the capture clock are only considered for the non common portions of the clock tree.
But the common path crosstalk contributions are considered for both the launch and the capture clock paths during setup analysis.
Noise Protection Techniques
1.Shielding: This method requires that shield wires are placed on either side of the critical signals. The shields are connected to power or ground rails.Shielding done only for critical nets.
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| Shielding |
2.Wire spacing: This reduces the coupling to the neighboring nets.
3.Guard ring: A guard ring in the substrate helps in shielding the critical analog circuitry from digital noise.4.Fast slew rate: A fast slew rate on the net implies that it is less susceptible to crosstalk and is inherently immune to crosstalk effects.
5.Increased the drive strength of victim net.
6.Decrease the drive strength of aggressor net.
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