FPGA Design Flow

The FPGA design flow is shown in the figure below:

Architecture design: This step involves analysis of the design requirements and functional simulation. The output of this step is a document which describes the design architecture, structural blocks, their functions and interfaces.Design engineer design the architecture according to system specification.

Design entry: The design is described in a formal hardware description language (HDL). The most common HDLs are VHDL and Verilog. Test environment design. This step involves writing of test environments and behavioral models. They are later used to ensure that the HDL description of a device is correct.

Behavioral simulation: This is an important step that check HDL correctness by comparing
output of the HDL model and the behavioral model.RTL description is used for simulation to test the functionality with the help of EDA tools.

Design Synthesis: In this step RTL code is converted to gate level netlist using synthesis tool.Netlist is a description of the circuit in terms of gates and connections between them.Synthesis is performed by a  synthesis tool. For an HDL code that is correctly written and simulated, synthesis shouldn't be any problem.However, synthesis can reveal some problems and potential errors that can not be found using behavioral simulation so an FPGA engineer should pay attention to warnings produced by the  synthesis tool.Functional verification is performed to ensure the RTL design is done according to the specifications.

Design Implementation: A  synthesis tool generate netlist is mapped onto particular device's internal structure. The main phase of the implementation step is place and route which allocates FPGA resources such as logic cells and connection wires.Then these configuration data are written to a special file by a program called bitstream generator.

Timing analysis: During the timing analysis timing tool checks whether the implemented design satisfies timing constraints such as clock frequency,setup violation and hold violation specified by the user.

SHARE

vlsi4freshers

Hi I’m Designer of this blog.