FPGA Interview Questions

1. What is FPGA?
FPGA Stands for Field Programmable Gate Array.FPGA is a semiconductor device containing programmable logic components called logic blocks, and programmable interconnects.

Logic blocks can be programmed to perform the function of basic logic gates such as OR,AND, and XOR, or more complex combinational functions such as decoders or  mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
Advantages of FPGA:
Faster time to market.
Ability to reprogram in the fiNeld to fix bugs.

2. Draw the general structure of FPGA.

3. Explain FPGA design flow.

4. What are DCM’s? Why they are used?

Digital clock manager (DCM) is a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature and voltage. That is clock output of DCM is stable over wide range of temperature and voltage, and also skew associated with DCM is minimal and all phases of input clock can be  obtained.
The output of DCM coming from global buffer can handle more load.

5. What is the purpose of a Phase lock loop(PLL)?

PLL stand for Phase locked loop and is commonly used inside FPGAs to generate desired clock frequencies. PLLs are built-in to the FPGA fabric and are able to take an input clock and derive a unique out-of-phase clock from that input clock. They are very useful if your design requires several unique clocks to be running internally.

6. What is the purpose of a DSP tile in an FPGA?

DSP stands for Digital Signal Processor but it is really a dedicated piece of hardware inside the FPGA that is very good at performing fast multiplication and addition operations. Normal FPGA logic is able to perform multiplies, but not at fast data rates of say 200 MHz or faster. This is where dedicated Digital Signal Processor(DSP) tiles are used. They are common in filter design or image processing pipelines that require many fast multiplication operations to be performed on input data.

7. What is the purpose of the synthesis tools?

The synthesis tools are provided by the FPGA vendor and are used to translate your VHDL or Verilog code into logic that the FPGA is built from example Flip-Flops, Look-Up Tables, Block RAMs, etc.

8. What is metastability, how would you prevent it?
Metastability means that a signal is in an unpredictable or unknown state. It occurs most often when bringing in a signal external to the FPGA into the internal logic. In general it should be avoided. There are several methods to prevent metastability inside your FPGA, a common suggestion is to "double-flop" all inputs into the local clock domain.

9. Explain differences between SRAM and DRAM.

SRAM means Static Random Access Memory, DRAM stands for Dynamic Random Access Memory. Both SRAM and DRAM are volatile,that means their information written to them is cleared when power is removed.
DRAM also needs to be refreshed in order to maintain the values written to it, where as SRAM being static does not need this.
The refreshing is usually handled by the memory controller. As far as use-cases, SRAM is better when there are short non-sequential reads and writes to memory required, and DRAM is better when there are large burst reads/writes of sequential memory.

10. What are differences between DLL and PLL?

PLL stand for Phase lock loop and DLL stand for Delay lock loop.

These are two technique to minimize the clock skew.

1. DLL have less clock skew as compare to PLL.

2. DLL have step errors but hybrid PLL does not have it.

3. PLL have voltage-controlled oscillator (VCO) and DLL use delay line.
4. PLL are hybrid analog and digital whereas DLL are all digital.

11. What are the differences between FPGA and CPLD?

FPGA:
1. SRAM based technology.
2. Must be reprogrammed once the power is off.
3. Usually used for complex logic circuits.
4. Costly
5. Segmented connection between elements.

CPLD:
1. Flash or EPROM based technology
2. Continuous connection between elements 
3. Usually used for simpler or moderately complex logic circuits.
4. Need not be reprogrammed once the power is off.
5. Cheaper

12. What is CLB and Slice?

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinational circuits. CLB are configurable logic blocks and can be configured to combo, ram or rom depending on coding style CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT. 
The memory assignment is a clocked behavioral assignment, Reads from the memory are asynchronous, and all the address lines are shared by the read and write statements.

13. Explain LUT and CLB of FPGA.

Look Up Table(LUT): Each slice contains four or six input look up table ,storage elements,multiplexers and carry logic. These elements are used to provide logic functions and arithmetic functions and ROM functions.
Configurable Logic Block(CLB): The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinational circuits. A CLB elements contain a pair of slices.They don't have direct connection to each other.

14. What is the purpose of DRC?

In ASIC there are some sets of rules which depends on technology used to design.They are parameters set aside by the concerned semiconductor manufacturer with respect to how the masks should be placed, connected, routed keeping in mind that variations in the fab process does not effect normal functionality.
In FPGA ,tool like Vivado check the correctness of the design before synthesis which is also said DRC check.

15. What are the different modes of programming the FPGA?
1.Flash

2.SRAM via JTAG or programmable cable.
3.USB and SD card.

16. What is minimum and maximum frequency of DCM in Spartan-3 series FPGA?

Spartan-3: Minimum frequency is 24 MHz and maximum frequency is 248 MHz.

17. Can a CLB configured as RAM?

Yes.In Xilinx CLB has two slices which is slice-L and slice-M.Function generators(LUT) in slice-M can be implemented as a synchronous RAM called distributed RAM.

18. Can you suggest some ways to increase clock frequency of design in FPGA?
1.Check critical path and optimize it.

2.Proper timing constraints.
3.Pipeline architecture.

19. What is the significance of FPGAs in modern day electronics?

1.Less time to Market when comparing with ASIC.
2.It is better for start-up companies to design their projects using FPGA rather than ASIC.
3.Less cost and reconfigurable as many require number of times.

20. What are the different reports we need to look while FPGA designing?

1. Synthesis report

2. Place and route report

3. Timing report after bit file generation.

In synthesis report we need to check signals or registers which are optimized and latches in design.

In PnR report and timing report we need to look Set Up and Hold violation and gate count and are clock constraints applied properly.
21. What are the inputs required for FPGA prototyping?

Inputs required for FPGA prototyping which synthesizable RTL design.

22. What is a Block RAM?
Block RAM is a specific part of an FPGA that is usually a 16k or 32k bits storage element. It can have dynamic width and depth and is useful for many applications inside of an FPGA. They are used in Dual-port memories, FIFOs, and LUTs.

23. What happens during place and route?
The synthesis process is usually followed by place & route which takes the primitives and places them inside the FPGA and checks that the entire design meets your timing constraints. The timing constraints tell the FPGA the clock rates and the specific I/O to use, and the place & route process ensures that your design is able to work at those speeds.
24. What are the different type of RAM in FPGA?

1.Distributed Memory: Array of register.

2.Block Memory: Dedicated memory
Synthesis tool use any memory depends on your coding.
1.When it require to make small amount of data  memory like small registers then use distributed memory.
2.When it require to make large amount of data  memory like large LUT then use block memory.Block memory depends on FPGA series.

25. What is the difference between a hard processor core and soft processor core?
1.Hard Processor Core: Some part of fpga has fixed block like processor core and other standard IPs and little space for other logic implementation.It can work on high speed due to better optimization.

2.Soft Processor Core: User need to implement soft processor core if required.Full FPGA can be used for logic implementation.It can be easily modified and have more logic.

26. Name of FPGA companies.
1.Xilinx
2.Altera
3.Microsemi
4.Lattice Semiconductor

27. How to generate clocks on FPGA?1.We need clock source regardless to drive FPGA

2.Inside we can use PLL to generate specific frequencies
3.We can use counters to scale down clock

28. What is synthesis?

Synthesis is the stage in the design flow which translating your Verilog code into gates.Synthesis tool gives a netlist of the design that you have synthesized that represents the chip which can be fabricated through an ASIC or FPGA vendor.
29. Draw a rough diagram of how clock is routed through out FPGA?
30. Tell me some of features of FPGA you are currently using?

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