Power consumption is a very huge challenge in modern day VLSI design. Various techniques have been proposed to control the power dissipation.
Power is drawn from a voltage source attached to the VDD pin of a chip.
Instantaneous power P(t) = Vdd * i(t)
Average power Pavg = E/T = ( ∫ Vdd *i(t) dt)/T
Instantaneous power P(t) = Vdd * i(t)
Average power Pavg = E/T = ( ∫ Vdd *i(t) dt)/T
Types of Power Dissipation
Dynamic power
Short‐circuit power
Static power
The source of these power dissipation are different so techniques are used to reduce the power is also different.
Dynamic Power
Dynamic power is required to charge and discharge load capacitance when transistors switch.When the input switches from 1 to 0 the PMOS transistor (PULL UP network) turns ON and charges the load to VDD. When the input switches from 0 to 1, the PMOS transistor turns off and the NMOS transistor is turned ON, and discharging the capacitor. One cycle involves a rising and falling output.
On rising output, charge Q = CVdd is required to charge the output node to Vdd.
On falling output, the load capacitor discharges to GND.
This repeats T * fsw times over an interval of T.
If the frequency of output switching is fsw, the charging and discharging cycle will repeat T*fsw time over a time interval T.
Calculation of average dynamic power:
Activity Factor
The activity factor is the probability that the circuit node transitions from 0 to 1 because that is only the time the circuits consume power.Glitches in the circuit can increase the activity factor. Activity factor is measure of how frequently output switching takes place.
The activity factor is the probability that the circuit node transitions from 0 to 1 because that is only the time the circuits consume power.Glitches in the circuit can increase the activity factor. Activity factor is measure of how frequently output switching takes place.
We can write: fsw = α.f ,where fsw is the switching frequency, f is the clock frequency, and α is the activity factor.
If the gate output directly drives the clock, α = 1.
If the gate output switches once per cycle, α = ½.
CMOS dynamic gates: Switches either 0 or 2 times per cycle, α = ½.
CMOS static gates: Design dependent, typically α = 0.1.
Taking into account the activity factor α, the dynamic power of the gate can be calculated as:
Pdynamic = α CV2DD f
Short Circuit Power
Short circuit power is some kind of power dissipation in a CMOS, when the signals transitions are taking place.Short circuit current occurs in a CMOS gate during signal transitions when both the nMOS and pMOS networks are ON and there is a direct path between VDD and GND. The current is flowing from VDD to VSS is also called cross-bar current.In modern day designs short circuit power can consume 20 percent of the total power dissipation.
It is related to frequency of switching.As clock frequency increases, the frequency of transitions increases.Thus short circuit power dissipation also increases.
Static Power
Static power is consumed even when a chip is not switching they leak a small amount of current.Leakage effects draw power from nominally OFF devices.
Various causes of leakage:
Sub‐threshold leakage.
Reverse biased p‐n junction.
Channel punch through.
Oxide leakage.
Hot carrier tunneling effect.
Drain induced barrier lowering.
Gate induced drain leakage.
As technology scales, static power dissipation becomes more and more important in terms of leakage power.
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Short circuit power is some kind of power dissipation in a CMOS, when the signals transitions are taking place.Short circuit current occurs in a CMOS gate during signal transitions when both the nMOS and pMOS networks are ON and there is a direct path between VDD and GND. The current is flowing from VDD to VSS is also called cross-bar current.In modern day designs short circuit power can consume 20 percent of the total power dissipation.
It is related to frequency of switching.As clock frequency increases, the frequency of transitions increases.Thus short circuit power dissipation also increases.
Static power is consumed even when a chip is not switching they leak a small amount of current.Leakage effects draw power from nominally OFF devices.
Various causes of leakage:
Sub‐threshold leakage.
Reverse biased p‐n junction.
Channel punch through.
Oxide leakage.
Hot carrier tunneling effect.
Drain induced barrier lowering.
Gate induced drain leakage.
As technology scales, static power dissipation becomes more and more important in terms of leakage power.
Click here for next part
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