Universal Verification Methodology (UVM) is a system verilog language based verification methodology which is widely used across VLSI industry. UVM is a methodology defined to build testbenches for verifying the design.UVM consist a defined methodology for architecting modular testbenches for the design verification. UVM has a library of the classes that helps in designing and implementing modular testbench components and stimulus.
Advantages
Re-use of testbench components
Development of Verification IP
Easier migration from simulation to emulation environment.
Sequence based stimulus generation.
Factory mechanisms.
UVM Testbench Architecture
Test: configuring the testbench. Initiate the testbench components construction process by building the next level down in the hierarchy example: environment(env). Initiate the stimulus by starting the sequence.
Environment: It is a container component for grouping higher level components like agent’s and scoreboard.
ScoreBoard: Receive data items from monitor and compare them with expected value.
Agent: UVM agent groups the uvm_components specific to an interface or protocol.
Sequence Item: It defines the pin level activity generated by agent (to drive to DUT through the driver).
Monitor: Observe the pin level activity on interface signal and converts into packet level which is sent to components such as scoreboard.
Driver: It receive the stimulus from generator and drive the packet level data inside the transaction into pin level to DUT.
Sequence: It defines the sequence in which the data items need to be generated and sent/received to/from the driver.
Sequencer: It is responsible for routing the data packets(sequence_item) generated in sequence to the driver or vice verse.
Generator: Generates different input stimulus to be driven to DUT.
Interface: Contains design signals that can be driven or monitored.
Basic Structure Of UVM
1. Testbench.svh: Testbench.svh is module that creates an object of test class passes on interface pointer and starts simulation using run_test()call.
Include all class definition,UVM packages and macros.
Clock generation logic.
Instantiate interface and pass to test top as virtual interface.
run_test().
2. Test.svh
Instantiate environment(env) , config and stimulus.
Build Phase
-Construct Env and Config.
-Get virtual interface handle from TB and pass it to env
Run Phase
Construct Sequence
Start Test
Pass sequence (seq) to sequence(sqr).
-raise objection
- seq.start(sqr)
-drop objection
3. Env.svh
Instantiate Agent.
Build Phase
-Pass virtual interface handle to agent after getting it from Test.
Add connect phase if scoreboard is present.
4. Sequence.svh
Parameterize to type "sequence item(seq_item)".
task body():once sequence started it gets executed.
-Instantiate seq_item
-construct seq_item
-start_item(seq_item);
-randomize();
-finish_item(seq_item);
5. seq_item.svh
Declare all transaction variables.
Implement "do_copy","convert2string" functions.
6. Agent.svh
Instantiate all components to be present in agent like driver ,sequencer and monitor.
Build phase
-construct all sub components instantiated above.
-Get virtual interface from env and pass it to all the sub components.
Connect phase-connect driver and sequencer port to export.
7. Sequencer.svh
Parameterize to type "seq_item"
Build phase
-Get virtual interface from agent
8. Driver.svh
Build phase
Get virtual interface from agent(parent) or config database.
Run Phase
forever begin
-get_next_item();(get seq_item from sequencer)
-item_done();(handshake done from driver to sequencer)
end
Other API's like "peek()","try_get()","put()" could also be used.
9. Monitor.svh
Analysis port: monitor writes transaction objects to this port once get detected at the interface.
Construct analysis port
Build Phase
-Get virtual interface handle from agent(parent) or config database.
Run phase
Code functionality
-construct transaction objects(seq_items).
-Tap signal at the interface through mod port.
-write transactions to analysis port.
10. Config.svh
If needed.
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