Digital Design Interview Questions Part 5

1. A cascade of three identical modulo - 5 counters has an over all modulus of
a) 5
b) 125
c) 25
d) 625
2. Consider the given circuit. In this circuit, the race around

a) does not occur

b) occurs when CLK=0

c) occurs when CLK=1 and A=B=1

d) occurs when CLK=1 and A=B=0

3. The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in Fig. is 10 KHz. The frequency of the signal available at Q is.

a) 10 KHz

b) 2.5 KHz

c) 5KHz

d) 20 KHz

4. For a J-K flip flop its J input is tied to its own Q output and its K input is connected to its own Q output. If the flip flop is fed with a clock of frequency 1 MHz its Q output frequency will be.

a) 1.5 MHz

b) 1 MHz

c) 0.5 MHz

d) None of the above

5. The current state Q A Q B of a two J K flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the J K flip-flop. The next state of the system is

a) 00

b) 01

c) 10

d) 11

6. Consider the following circuit which uses a 2:1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of A and B is

a) A⊕B

b) (A+B)'

c) A+B

d) (A⊕B)'

7. In the 4 × 1 multiplexer, the output F is given by F = A ⊕ B.Find the required input I3 I2 I1 I0.

a) 1110
b) 1000
c) 0110
d) 1010
8. The output  Y  of the logic circuit given below is

a) 1
b) 0
c) X
d) X'

9. Figure shows a  4:1   M U X  to be used to implement the sum  S of a 1 -bit full adder with input bits  P  and  Q  and the carry input  Cin.  Which of the following combinations of inputs to  I0,I1,I2  and I3  of the mux  will realize the sum  S.

a) I0=I1=Cin and I2=I3=Cin'

b) I0=I1=Cin' and I2=I3=Cin

c) I0=I3=Cin' and I1=I2=Cin'

d) I0=I3=Cin' and I1=I2=Cin

10. In the figure, as long as  X1 = 1  and  X2 = 1 the output  Q  remains.

a) at 0

b) at 1

c) unstable

d) at its initial value

11. The digital circuit using two inverters shown in figure will act as

a) a bi-stable multi-vibrator

b) a astable multi-vibrator

c) a monostable multi-vibrator

d) None of the above

12. The  2' s  compliment representation of the decimal value (-15 )is

a) 1111

b) 11111

c) 10001

d) None of the above

13. In the circuit shown, A & B are the inputs, and F is the output. What is the functionality of the circuit?

a) Latch

b) XOR

c) XNOR

d) SRAM Cell

14. In the circuit shown, the clock frequency, i.e. the frequency of CLK signal is 12 kHz. The frequency of the signal at Q2 is.

a) 5 KHz

b) 4 KHz

c) 6 KHz

d) 12 KHz

15. For the component in the sequential circuit shown below, tpd is the propagation delay tsetup is the setup time and thold is the hold time. The maximum clock frequency (rounded off to the nearest integer) at which the given circuit can operate reliably is.

Solution: In any sequential circuit, the condition for proper operation is

16. The figure below shows a multiplexer where S1 and S0 are the select lines, I0 to I3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output F is

a) PQ+Q'R

b) PQ'R+P'Q

c) P+QR'

d) Q'+PR

Answers: 1. b  2. a  3. c  4. c  5. d  6. d  7. c  8. a  9. c  10. c  11. a  12. c  13. c  14. b 15. 76.92 KHz  16. a

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