1. In a CMOS circuit, if the frequency of operation is doubled, the power supply voltage is divided by 2, and load capacitance is increased 4 times, then the dynamic power consumption will increase by.
a) 4 times
b) 2 times
c) 8 times
d) None of the above.
2. Short-circuit power is consumed in a CMOS gate when
a) One of the transistors has a stuck-on fault.
b) The inputs of the gate changes state.
c) Both the pull-up and pull-down networks are conducting.
d) None of the above.
3. If 0.65 is the probability that the output of a gate is 1, the activity factor of the gate output will be
a) 0.25
b) 0.21
c) 0.22
d) 0.24
4. If 0.5, 0.65, 0.3 and 0.75 denote the probabilities that the inputs of a 4-input AND gate are at logic 1, then the probability that the gate output is at logic 0 is given by
a) 0.92
b) 0.85
c) 0.90
d) None of the above
5. What do you mean by glitch?
a) Change in circuit delay due to variations in the critical path.
b) Spurious transition in the output of a circuit due to unbalanced path delays.
c) A sudden change in the frequency of a clock signal.
d) None of the above
6. Which of the following is/are true for clock gating?
a) It helps in reducing power consumption.
b) It helps in avoiding race conditions.
c) It is desirable from the point of view of testability.
d) All of the above.
7. If the output of a gate switches once every 2 cycles, the activity factor will be
a) 0.26
b) 0.24
c) 0.22
d) 0.25
8. Which of the following can result in a reduction in power dissipation?
a) Use a longer bus.
b) Segment a bus into several buses.
c) Use buffers while interfacing devices to the bus.
d) None of the above
9. In RTL level design, which of the following can lead to a reduction in power dissipation?
a) Using gating signal to disable a module when it is not being used.
b) Partition a memory module into a number of smaller modules.
c) Reordering the datapath.
d) All of the above.
10. For FSMs, clock gating can help in reducing power dissipation in cases where
a) The present state and next state are the same.
b) The FSM runs repeatedly in a loop.
c) The difference in bits in the encoding of present and next states is 1.
d) None of the above.
11. Consider a bus connecting two or more modules. Segmenting the bus into several buses shall result in
a) Reduction in the parasitic capacitance.
b) Increase in the parasitic capacitance.
c) Reduction in switching capacitance because of decrease in fanout.
d) None of the above.
12. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is
a) 1 or Vdd
b) 0 or gnd
c) High Impedance(Z)
d) None of the above
12. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is
a) 1 or Vdd
b) 0 or gnd
c) High Impedance(Z)
d) None of the above
Answers: 1.b 2.c 3.c 4.a 5.b 6.a 7.d 8.b 9.d 10.a 11.c 12.c
Hi
ReplyDeleteCould you explain the answer of Q.3 please?
The activity factor of a gate is defined as
DeleteP (1 – P), where P is the probability that the node is at logic 1.
In this case, the activity factor = 0.65 (1 – 0.65) = 0.227
Hi can you please explain the logic involved in solving of question 4?
ReplyDeleteThe output of an AND gate is 0 only when all the inputs are not at 1.
DeleteThis probability can be expressed as: 1 – (0.5 x 0.65 x 0.3 x 0.75) = 0.92