These type of questions asked in written test or online test of product and service based companies like synopsys, nvidia, cadence, nxp, mentor graphics, qualcomm, xilinx, amd and intel etc.
1. CRPR stands for.
1. CRPR stands for.
a) Clock reconvergence past removal.
b) Cell reconvergence pessimism removal.
c) Clock reconvergence present removal.
d) Clock reconvergence pessimism removal.
2. Which points are true for a “Net”:
a) It is a wire connecting pins of standard cells and blocks
b) It can be broken up into segments for equivalent electrical representation
c) It can travel on multiple metal layers of the chip
d) All of the above
3. Which of the following points are true for a setup check?
a) Tpd + Tcomb < Tcp – Ts
b) Total data path delay = Tpd + Tcomb
c) Setup check limits the data path to a maximum value
d) All of the above
4. In STA, delay is a function of
a) P, V, T
b) Slew_in and load
c) Slew_in, load, P, V, T
d) None of the above
5. The time available between the asynchronous signal going to inactive to the active clock edge is _____ and the time between active clock edge and asynchronous signal going inactive is _______.
a) Recovery Time, Removal Time
b) Removal Time, Recovery Time
c) Setup Time, Hold Time
d) Hold Time, Setup Time
6. Which points are true for Pre-Layout STA
i) No information about the nets
ii) Estimated net delays
iii) Back annotated net information
iv) Clock network fully implemented
a) i), iii), and iv)
b) i) and ii)
c) i), ii), and iii)
d) iii) and iv)
7. Cell delay is generally a function of
a) Input delay and output delay
b) Input transition and output load
c) Input capacitance and output transition
d) Input load and output load
8. What are the different formats that Parasitic are extracted from a layout?
a) DSPF
b) SPEF
c) Both a and b
d) None of the above
9. Net capacitive load is
a) Sum of pin capacitance loads of every fan-out of the net
b) Square of sum of pin capacitance loads of every fan-out of the net
c) Average of pin capacitance loads of every fan-out of the net
d) None of the above
10. Calculate the Slack for the following figure, if Tsetup of capture flop = 3ns
a) 9ns
b) 8ns
c) 7ns
d) 6ns
11. Virtual clock exists but is not associated with any pin or port. It is used as a reference in STA analysis to specify input and output delays relative to a clock.
a) True
b) False
12. If a path exists between two multiplexed logic blocks that are never selected at the same time, then that path is considered as
a) Critical Path
b) False Path
c) Multi-Cycle Path
d) None of the above
13. In On-Chip variation (OCV) Mode, for Setup check, EDA tool uses ____delays for the launch clock path and data path, _____ delays for capture clock path.
a) Maximum, Minimum
b) Minimum, Maximum
c) Maximum, Maximum
d) Minimum, Minimum
14. For the figure shown below, calculate the minimum clock period
a) 5.46ns
b) 5.47ns
c) 5.48ns
d) 5.49ns
15. There is a timing path between d and clk in D flip flop.
a) True
b) False
16. There is a timing path between d and clk in D latch.
a) True
b) False
17. Clock re-convergence pessimism is an accuracy limitation that occurs when
a) Two different clock paths partially share a common physical path segment and the shared segment is assumed to have a minimum delay for one path and maximum delay for other path
b) Two different clock paths partially share a different physical path segment and each segment is assumed to have a minimum delay for one path and maximum delay for other path
c) Both a and b
d) None of the above
18. In operating conditions, Interconnect model type defines
a) RC tree topology that EDA tool uses to estimate net capacitance and resistance during pre-layout analysis
b) Interconnect delays
c) Cell delays
d) None of the above
19. For each setup relationship, what type of hold checks will be performed by PrimeTime?
a) The data launched by the setup launch edge must not be captured by the previous capture edge
b) The data launched by the next launch edge must not be captured by the setup capture edge
c) Both a and b
d) None of the above
20. For the following figure, what is the Elmore delay equation.
a) Σ(i=1,N)Ci(Σ(j=1,i)Rj)
b) Σ(i=1,N)Ci(Σ(j=1,i)Rj+1)
c) Σ(i=1,N)Ci(Σ(j=1,i)Rj - 1)
d) Σ(i=1,N)Ci(Σ(j=1,i)Rj/1)
21. Wireload models are used to estimate
a) Resistance and Capacitance
b) Area overhead due to interconnect
c) Length of the net based on number of fan-outs
d) All of the above
22. Arrival time defines
a) The time interval during which a data signal can arrive at a pin in relation to the last edge of the clock signal that triggers the data transition
b) The time interval during which a data signal can arrive at a pin in relation to the nearest edge of the clock signal that triggers the data transition
c) The time interval during which a data signal can arrive at a pin in relation to the nearest edge of the clock signal that will not trigger the data transition
d) The time interval during which a data signal can arrive at a pin in relation to the last edge of the clock signal that will not trigger the data transition
23. In delay calculations, Gate delays are taken from ___ and Net delays are taken from ___.
a) PVT , Wire load
b) Post layout data, Libraries
c) Libraries, Post layout data
d) Wire load, PVT
Answers: 1.d 2.d 3.d 4.c 5.a 6.b 7.b 8.c 9.a 10.d 11.a 12.b 13.a 14.d 15.b 16.a 17.a 18.a 19.c 20.a 21.d 22.b 23.c
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