These
type of questions asked in written test or online test of product and service
based companies like synopsys, nvidia, cadence, nxp, mentor graphics, qualcomm,
xilinx, amd and intel etc.
1. Chip utilization depends on
1. Chip utilization depends on
a) Only standard cells.
b) Standard cells and macros.
c) Only macros.
d) Standard cells,macros,I/0 pads.
2. Decap cell is used
a) To avoid the dynamic IR drop.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.
3. Pitch of the wire is
a) Min width.
b) Min width+min spacing.
c) Min spacing.
d) Min width-min spacing.
4. Which of the following is best suited for CTS?
a) CLKBUF
b) BUF
c) INV
d) None of the above
5. Which of the following is not present in SDC?
a) Max Cap
b) Max fan
c) Max tran
d) Max current density
6. Max voltage drop will be there at (without macros)
a) Middle
b) Left and right sides
c) Bottom and Top sides
d) None of the above
7. Which of the following is having highest priority at final stage (post routed) of the design?
a) Setup violation
b) Skew
c) Hold Violation
d) None of the above
8. The solution for antenna effect is
a) Shielding
b) Buffer insertion
c) Diode insertion
d) Double spacing
9. Maximum current density of a metal is a available in
a) .lib
b) .tf
c) .v
d) .sdc
10. Fillers cells are added
a) Before placement of std cells
b) After placement of std cells
c) Before floor planning
d) Before detail routing
11. Abutted design has
a) No gap between blocks.
b) Gap between the blocks.
c) Both a and b
d) None of the above
12. Routing congestion can be avoided by
11. Abutted design has
a) No gap between blocks.
b) Gap between the blocks.
c) Both a and b
d) None of the above
12. Routing congestion can be avoided by
a) Distributing cells.
b) Placing cells closer.
c) Placing cells at corners.
d) None of the above
13. What violations solved in LVS?
b) Placing cells closer.
c) Placing cells at corners.
d) None of the above
13. What violations solved in LVS?
a) Shorts.
b) Opens.
c) Missing text layers.
d) All of the above
14. Search and repair is used for
a) Reduce EM violations.
b) Reduce IR drop.
c) Reduce DRC.
d) None of the above
15. Static power can be reduced by placing
a) LVT cells
b) SVT cells
c) HVT cells
d) None of the above
16. What is the effect of high drive strength buffer when added in long net?
a) Delay on net decreases.
b) Capacitance on net increases.
c) Delay on net increases.
d) Distance on the net increases.
17. Major importance of power plan is
a) IR drop.
b) Electromigration
c) Both a and b
d) None of the above
18. The metal area and(or)perimeter of conducting layer/gate to gate area is called
a) Aspect ratio
b) OCV
c) Antenna ratio
d) Utilization
19. Halo allows the placement of
a) Only standard cells
b) Only macros
c) Only buffers and inverters
d) None of the above
20. Routing congestion is
a) Available tracks are less than required tracks.
b) Depends on the routing layers available.
c) Required tracks are less than available tracks.
d) None of the above
21. Which of the following is preferred while placing macros?
a) Macros placed left and right side of die.
b) Macros placed center of the die.
c) Macros placed top and bottom side of die.
d) Macros placed based on the connectivity of the I/O.
22. More IR drop due to
a) Increase in metal width
b) Decrease in metal length
c) Increase in metal length
d) None of the above
22. More IR drop due to
a) Increase in metal width
b) Decrease in metal length
c) Increase in metal length
d) None of the above
23. Capacitance table can be created by
a) .tf file
b) .lib file
c) lef file
d) .sdc
24. Why do we to remove scan chains before placement?
a) Because scan chains are group of flip flop
b) It does not have timing critical path
c) It is series of flip flop connected in FIFO
d) None of the above
25. What are preroutes in your design?
a) Power routing
b) Signal routing
c) Both a and b
d) None of the above
26. Clock tree doesn't contain following cell
a) Clock buffer
b) Clock inverter
c) AOI cell
d) None of the above
27. What is the goal of CTS?
a) Minimum IR drop
b) Minimum EM
c) Minimum Skew
d) Minimum Slack
a) Minimum IR drop
b) Minimum EM
c) Minimum Skew
d) Minimum Slack
Answers: 1.b 2. a 3. b 4. a 5. d 6. a 7. c 8. c 9. b 10. d 11. a 12. a 13. d 14. c 15. c 16. a 17. c 18. c 19. c 20. a 21. d 22. c 23. c 24. b 25. a 26. c 27. c
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