Verilog Interview Questions Part 3

1. What logic is inferred when there are multiple assign statements targeting the same wire?

• It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source.

2. What do conditional assignments get inferred into?

• Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexer. For example, the following is the code for a simple multiplexer:

wire wire1;

assign wire1  =  (sel ==  1'b1)  ?  a  :  b;

3. Why should a non-blocking assignment be used for sequential logic, and what would happen if a blocking assignment were used? Compare it with the same code in a combinational block.

• The main difference between the blocking and non-blocking assignment is that, in the blocking assignment, the RHS immediately gets assigned to the LHS, whereas for the nonblocking assignment, the assignment to the LHS is scheduled after the RHS is evaluated.

Using blocking statements in a sequential logic

The following is an example of a Verilog module in which the blocking assignments have been used in the sequential block.

In the above example, the assignments to the reg1, reg2, reg3, out1 have been made as blocking assignments. The synthesized result is a single FF, with the d input of in1, and q output of reg3, as shown in the following figure:

This is because the intermediate results between in1 and out1 were stored in reg1, reg2, and reg3 in a blocking format. As a result, the evaluation of the final result to out1 didn’t require waiting for all the events of the RHS to be completed. Rather, they were immediately assigned to the LHS in the order specified. Observe that the signals reg1, reg2, and reg3 have been optimized away by synthesis.

Using nonblocking statements in a sequential logic
The following illustration of code uses the nonblocking assignments in a sequential block:

In the above example, the assignments to the reg1, reg2, reg3, out1 have been made as nonblocking assignments. The synthesized result is the inference of as many FFs as specified in the always block [in this case, 4 FFs].

This is because the intermediate results between in1 and out1 were stored in reg1, reg2, and reg3 in a nonblocking format. As a result, the evaluation of the result to each individual reg required waiting for all the events of the RHS to be completed. In this case, it was the output of the previous register controlled by the clk event. As a result, the output is a shift register.

Using blocking statements in a combinational logic

The following example illustrates the use of blocking statements in combinational logic:

In the above example, the blocking assignments are made in a combinational block. Note the absence of posedge and “<=”, being replaced with “=”, in the assignments. The logic synthesized out of this is a simple wire between in1 to out1.

This is because all the assignments have been immediate, and there is no event to wait upon.

4. What are some reusable coding practices for RTL Design?

A reusable design mainly helps in reducing the design time of larger implementations using IPs.

• Register all the outputs of crucial design blocks. This will make the timing interface easy during system level integration.
• If an IP is being developed in both Verilog and VHDL, try to use the constructs that will be translatable later into VHDL.
• Partition the design considering the clock domains and the functional goals.
• Avoid instantiation of technology specific gates.
• Use parameters instead of hard-coded values in the design.
• Avoid clocks and resets that are generated internal to the design.
• Avoid glue logic during top level inter-module instantiations.

5. Can the generate construct be nested?

• No. The generate construct cannot be nested. It is a syntax error to try to nest the generate-endgenerate construct.
• However, the if, case, and for constructs within the generate endgenerate can be nested. The constructs can also be used within one another, too, that is, if within case, for within if etc.
• You can also use multiple non-nested generate-endgenerate constructs within the module.

6. Why is one-hot encoding preferred for FSMs designed for high-speed designs?

• Since there is one explicit FF per stage of a one-hot encoded state machine, there is no need of output state decoding. Hence, the only anticipated delay is the clock to q delay of the FF. This makes the one-hot encoding mechanism preferable for high-speed operation.

7. Discuss the main differences between $strobe and $monitor.

The differences between $strobe and $monitor are summarized in the following points:

• $strobe can be used to create new simulation events, simply by encapsulating the $strobe system call within a simulation construct that moves simulation time, such as @(posedge clock), @(negedge clock),@(any_signal) etc.There can exist multiple $strobe system calls at the same time, with identical or different arguments.
• $monitor stands alone. A given set of arguments of $monitor form their own unique sensitivity list. Only one $monitor call can be active at any time. Each call to $monitor replaces any previous call(s) to $monitor.

8. How can I selectively enable or disable monitoring?

• $monitor can be selectively enabled or disabled by the $monitoron and the $monitoroff system calls, respectively. The $monitoron and $monitoroff system calls affect only the most recent call to $monitor.

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vlsi4freshers

Hi I’m Designer of this blog.