Q1. How the transfer characteristic of a CMOS NAND gate is affected with increase in fan-in?
Ans: Transfer characteristic does not remain symmetric with increase in fan-in of the NAND gate. The inversion voltage moves towards right with the increase in fan-in.
Q2. How switching characteristic of a CMOS NAND gate is affected with increase in fan-in?
Ans: When the load capacitance is relatively large, the fall time increases linearly with the increase in fan-in and the rise time is not affected much.
Q3. How noise margin of a CMOS NAND/NOR gate is affected with increase in fan-in?
Ans: Because of the change in the inversion voltage, the noise margin is affected with the increase in fan-in. For equal fan-in, noise margin is better for NAND gates compared to NOR gates. We may conclude that for equal area design NAND gates are faster and better alternative to NOR gates.
Q4. Give the AOI realizations for the sum and carry functions of a full adder.
Q5. How do you realize pseudo nMOS logic circuits. Compare its advantage and disadvantages with respect to standard static CMOS circuits.
Ans: In the pseudo-nMOS realization, the pMOS network of the static CMOS realization is replaced by a single pMOS transistor with its gate connected to GND. An n-input pseudo nMOS requires n+1 transistors compared to 2n transistors of the corresponding static CMOS gates. This leads to substantial reduction in area and delay in pseudo nMOS realization. As the pMOS transistor is always ON, it leads to static power dissipation when the output is LOW.
Q6. What are the advantages and limitations of pass transistor logic circuits? How the limitations are overcome?
Ans: Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in the realization. All the transistors can be of minimum dimension.Lower area due to smaller number of transistors in pass transistor realization compared to static CMOS realization. Pass transistor realization also has lesser power dissipation because there is no static power and short-circuit power dissipation in pass transistor circuits.The limitations are (a) Higher delay in long chain of pass transistors (b) Multi-threshold Voltage drop (Vout = Vdd – Vtn) (c) Complementary control signals and (d) Possibility of sneak path because of the presence of path to Vdd and GND.
Q7. What is charge leakage problem of dynamic CMOS circuits? How is it overcome?
Ans: The source-drain diffusions form parasitic diodes with the substrate. There is reverse bias leakage current .The current is in the range 0.1nA to 0.5nA per device at room temperature and the current doubles for every 10°C increase in temperature. This leads to slow but steady discharge of the charge on the capacitor, which represent information. This needs to be compensated by refreshing the charge at regular interval.
Q8. Explain the clock skew problem of dynamic CMOS circuits?
Ans: Clock skew problem arises because of delay due to resistance and parasitic capacitances associated with the wire that carry the clock pulse and this delay is approximately proportional to the square of the length of the wire. When the clock signal reaches a later stage before its preceding stage, the precharge phase of the preceding stage overlaps with the evaluation phase of the later stage, which may lead to premature discharge of the load capacitor and incorrect output during evaluation phase.
Q9. Distinguish between standby and runtime leakage power. Why runtime leakage power is becoming important in the present day context?
Ans: Standby leakage power dissipation takes place when the circuit is not in use, i.e. inputs do not change and clock is not applied. On the other hand, runtime leakage power dissipation takes place when the circuit is being used.
Q10. Explain the basic operation of a 2-phase dynamic circuit?
Ans: The operation of the circuit can be explained using precharge logic in which the output is precharged to HIGH level during f2 clock and the output is evaluated during f1 clock.
Ans: Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in the realization. All the transistors can be of minimum dimension.Lower area due to smaller number of transistors in pass transistor realization compared to static CMOS realization. Pass transistor realization also has lesser power dissipation because there is no static power and short-circuit power dissipation in pass transistor circuits.The limitations are (a) Higher delay in long chain of pass transistors (b) Multi-threshold Voltage drop (Vout = Vdd – Vtn) (c) Complementary control signals and (d) Possibility of sneak path because of the presence of path to Vdd and GND.
Q7. What is charge leakage problem of dynamic CMOS circuits? How is it overcome?
Ans: The source-drain diffusions form parasitic diodes with the substrate. There is reverse bias leakage current .The current is in the range 0.1nA to 0.5nA per device at room temperature and the current doubles for every 10°C increase in temperature. This leads to slow but steady discharge of the charge on the capacitor, which represent information. This needs to be compensated by refreshing the charge at regular interval.
Q8. Explain the clock skew problem of dynamic CMOS circuits?
Ans: Clock skew problem arises because of delay due to resistance and parasitic capacitances associated with the wire that carry the clock pulse and this delay is approximately proportional to the square of the length of the wire. When the clock signal reaches a later stage before its preceding stage, the precharge phase of the preceding stage overlaps with the evaluation phase of the later stage, which may lead to premature discharge of the load capacitor and incorrect output during evaluation phase.
Q9. Distinguish between standby and runtime leakage power. Why runtime leakage power is becoming important in the present day context?
Ans: Standby leakage power dissipation takes place when the circuit is not in use, i.e. inputs do not change and clock is not applied. On the other hand, runtime leakage power dissipation takes place when the circuit is being used.
Q10. Explain the basic operation of a 2-phase dynamic circuit?
Ans: The operation of the circuit can be explained using precharge logic in which the output is precharged to HIGH level during f2 clock and the output is evaluated during f1 clock.
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