Digital Design Interview Questions Part 6

1. A two binary multipliers can be implemented using.

a) 2 input AND gates only

b) 2 input XOR gates and 2 input AND gates only

c) Two 2 input NOR gates and 1 XOR gate

d) XOR gates and shift registers

2. The device which changes from serial data to parallel data is

a) Counter

b) Multiplexer

c) Demultiplexer

d) Flip Flop

3. The gates required to build a half adder are

a) EXOR gate and NOR gate

b) EXOR gate and OR gate

c) EXOR gate and AND gate

d) None of the above

4. Which of the following logic gates can be used to realize all possible combinational logic functions.

a) OR gate

b) XOR gate

c) Universal gates

d) XNOR gate

5. A carry look ahead adder is a parallel carry adder where all sum digits are generated by directly from the input digits.

a) True

b) False

6. How many minimum numbers of 2:1 multiplexer required to implement half subtractor ?

a) 4

b) 3

c) 1

d) 2

7. What are the minimum number of 2:1 multiplexer required to generate a 2 input AND gate and 2 input EXOR gate?

a) 1 and 2

b) 1 and 3

c) 1 and 1

d) 2 and 2

8. What will be the output of following circuit,

a) AB'C+ABC'

b) ABC+AB'C'

c) A'BC+A'B'C'

d) A'B'C+A'BC'

9. The minimum number of 2:1 multiplexer required to realize a 4:1 multiplexer is

a) 4

b) 3

c) 2

d) 1

10. What will be the output of following circuit,

a) F=AC

b) F=AC'+A'C

c) F=BC

d) F=A+C

11. What will be the output of following circuit,

a) F = AND(P,Q)

b) F = OR(P,Q)

c) F = XNOR(P,Q)

d) F = XOR(P,Q)

12. What will be the output of following circuit,

a) WS1'S2'

b) W'+S1+S2

c) WS1+WS2+S1S2

d) W^S1^S2

Answers: 1.b  2.c  3.c  4.c  5.a  6.d  7.a  8.a  9.b  10.b  11.d  12.d

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