1.Capacitor used as memory element in which kind of memory.
a) DRAM
b) SRAM
c) ROM
d) None of the above
2. Which is fastest memory in all of these memories?
a) DRAM
b) SRAM
c) ROM
d) None of the above
3. Smallest storing element of SRAM is called
a) Resistor
b) Flip Flop
c) Bit Cell
d) Capacitor
4. Which are the storing node in this bit cell in?
a) M1 and M2
b) BL and BLB
c) Q and QB
d) M3 and M4
5. The maximum amount of DC noise that can be tolerated by the cross coupler inverter pair such that the bit cell retains its data?
a) Write noise margin
b) Read Voltage
c) Write trip point
d) Static noise margin
6. Bit cell ratio is defined as
a) Ratio of pull down transistor to pull up transistor
b) Ratio of pull down transistor to access transistor
c) Ratio of pull up transistor to access transistor
d) Ratio of access transistor to pull down transistor
7. What is correct order size of Bit Cell transistor?
a) M1,M2,M5
b) M2,M5,M1
c) M1,M5,M2
d) M5,M2,M1
8. Why we need to pre charge bit line before read operation?
a) To reduce power
b) To ensure a specific voltage
c) To make it floating
d) To make fast read operation
9. If array size is 32x256 and mux factor is 4,what would be word size?
a) 32
b) 64
c) 128
d) 256
10. If we have to design 1KB memory how many arrays do we need to design size of 32x 32?
a) 4
b) 8
c) 6
d) 16
11. In DRAM why we need to refresh data after few moment?
a) Because of leakage of ground
b) Because of leakage of pass transistor
c) Because of leakage of storing capacitor
d) None of the above
12. How we are refreshing data in DRAM?
a) By pre charging
b) By pre discharging
c) By repeated read operation
d) By repeated write operation
13. Why we use sense amplifier in SRAM?
a) To make fast read operation
b) To save the power
c) To write data in memory
d) To sense data during read time
14. Access time define in memory
a) Minimum amount of time required to read a bit of data from the memory
b) Minimum amount of time required to write a bit of data in the memory
c) Minimum amount of time required to read and write a bit of data to the memory
d) None of the above
15. How we can reduce variation in sense amplifier?
a) Using HVT devices
b) Using ULVT devices
c) Using SVT devices
d) To increase gate size of input devices of sense amplifier
16. How we can reduce leakage current of SRAM memory?
a) Decrease power supply
b) By decreasing wire capacitance
c) By using high VT cell
d) By using power gating
17. What is offset for a sense amplifier?
a) Minimum voltage on bit lines
b) Minimum differential voltage at input nodes of sense amplifier to give correct output
c) Maximum differential voltage at input nodes of sense amplifier to give correct output
d) Maximum voltage on bit lines
18. How we are deciding word line driver sizing?
a) On the basis of load of access transistor size of array
b) On the basis of load of pull down transistor size of array
c) On the basis of pull up transistor of array
d) None of the above
19.The difference between VDD and maximum bit line voltage required to flip the data storage nodes Q and QB is called.
a) SNM
b) WNM
c) WSNM
d) Pre charge voltage
20. What are the advantages and disadvantages of DRAM when compared to SRAM?
Answer: DRAM has 3 main advantages over SRAM:
1.DRAM memory cell (1 transistor and capacitor) is simple and smaller than SRAM (6 transistors).DRAM has more density (more cells per chip). The larger memories are always made of made of DRAMs only. ( Main memory)
2.DRAM is cheaper than SRAM.
3.DRAM dissipates lesser power.
Disadvantages:
1.DRAM is slower than SRAM. Where speed is critical, SRAM will be used. Example: Cache memory
2.DRAM requires periodic refreshing.
3.SRAM is compatible with CMOS technology whereas DRAM is not.
Answers: 1.a 2.b 3.c 4.c 5.d 6.b 7.b 8.b 9.b 10.b 11.c 12.c 13.a 14.a 15.d 16.c & d 17. b 18.a 19.b
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