1.The dynamic response e.g. switching speed of MOS system are strongly dependent on the:
A) Parasitic capacitances and Interconnect
capacitances
B) I/P capacitances
C) Load capacitances
D) All of the above
2. At absolute zero, Si act as a:
A) Non - metal
B) Metal
C) Insulator
D) None of these
3. If A and B are the two 1 - bit Numbers, what logic gate will be needed to test for A=B?
A) NOR
B) XOR
C) Inclusive NOR
D) None of these
4. Reducing the supply voltages of CMOS circuit causes:
A) Increase of propagation delay
B) Decrease of noise Immunity
C) Decreasing In power dissipation
D) All of the above
5. If a clock with time period T sec is applied to an N-stage shift to register the output of the final stage will be displayed by,
A) nT sec
B) (n-1)T sec
C) n/T sec
D) None of these
6. A Schmitt trigger has VT+ = 2.0V and VT- = 1.2V. What is the hysteresis voltage of the Schmitt trigger?
A) 0.4 volt
B) 0.6 volt
C) 0.8 volt
D) 1.2 volt
7. Which of the following has the advantage of both less power of dissipation and faster speed.
A) BiCMOS
B) CMOS
C) TTL
D) ECL
8. In an R-2R ladder D/A converter, the input resistance is
A) Not same for all digital inputs
B) R for each input
C) 2R for each input
D) 3R for each input
9. If the ratio of concentration of electrons that of holes in a semiconductor is 13/8 and the ratio of currents is 7/3 then what is the ratio of their drift velocity ?
A) 3/13
B) 13/7
C) 3/8
D) 8/3
E) None of these
10. In a digital reproduction of an analog curve, accuracy can be increased by __.
A) sampling the curve more often
B) sampling the curve less often
C) Decreasing the number of bits used to
represent each sampled value
D) All of the above
11. The problem that occurs when the date input to register does not obey the setup time and hold time is
A) Glitches
B) Clock - race
C) Cycle - stealing
D) None
12. The No of transistor switches are direct coupled Rise & fall times of cascade will
A) Increase linearly
B) Increase exponentially
C) Not increases
D) Get longer slowly
13. A depletion type NMOS is operated in enhancement mode Vp = -4 volts. For Vgs = +3 volts,as VDS is increased, ID becomes nearly constant when VDS equals.
A) 1 volt
B) 3 volt
C) 4 volt
D) 7 volt
14. Field effect transistors, compared with bipolar transistors
A) Have small input resistance
B) Have small noise coefficient
C) The current is at the same time conditioned by
electrons and holes.
D) Provide current amplification
E) The performance is mainly conditioned by injection of minority carriers.
15. Given the function: F(A,B,C,D) = å(0,2,4,5,6,7,8,10,13,15), write down the simplified minimal function.
A) A’(B+C’) + BD + AB’D’
B) A’B+A’D’+AB’D’
C) A’C+B’D+CD
D) A’B+BD+B’D’
E) B(A+C’)+CD+AC
F) None of these
16. The minimum number of flip-flops required to construct a counter that counts as follows, are 0 7 48 129 240 512 1024 0 7 …
A) 5
B) 10
C) 8
D) 4
E) 3
F) 7
17. What data violates setup time of a Delay Flip flop, which of the following is true
A) Flip flop stays at
previous state.
B) Flip flop goes to high
impedance state “Z”
C) Flip flop goes to
unknown state
D) Flip flop delay increases
18. Which of the following statements are true ?
A) PMOS transistor
transfers 1 without any degradation and 0 with degradation
B) NMOS transistor
transfers 0 without any degradation and 1 with degradation
C) Transmission gate passes
1 and 0 equally well
D) All of the above
19. What is the simplified Boolean equation of the following Kamaugh map ?
0 0 0 0
0 0 1 0
1 1 1 1
0 1 1 1
A) AAB+AC+AD+BCD
B) BC+BD+ABD
C) ABC+BCD+AC
D) None of the above
20. Determine odd parity for each of the following date words.
1011101 11110111 1001101
A) P = 1, P = 1, P = 0
B) P = 0, P = 0, P = 0
C) P = 1, P = 1, P = 1
D) P = 0, P = 0, P = 1
21. With fall of temperature, the forbidden energy gap of a semiconductor.
A) Increases
B) Decreases
C) Remains unchanged
D) Sometime increases and sometimes decreases
22. The No. of 4 line to 16 decoder required to make an 8 line to 256 decoder is.
A) 16
B) 17
C) 32
D) 64
23. Which of the following pair can’t be considered as a universal gate ?
A) Multiplexor and inverter
B) OR gate and inverter
C) XOR gate and inverter
D) Half adder and inverter
24. Which stage is of a d.c. power supply uses Zener diode
A) Rectifier
B) Voltage divider
C) Filter
D) Regulator
25. The sums of A and b in a half adder can be implemented by using “K” NAND gates. The value of K is
A) 3
B) 4
C) 5
D)None of these
26. A design is having setup violation of -200ps and hold violation of -100ps for a clock whose period is 1000ps. If the clock period is increased to 1100ps, what is the expected setup and hold violation respectively?
A) -100ps and 0ps
B) -300ps and -200ps
C) -100ps and -100ps
D) -100ps and -200ps
27. What do you mean by Class-AB Amplifier ?
A) O/p transistor conducts
for full 180 degrees of input waveform.
B) O/p transistor conducts
for 360 degrees of input waveform.
C) O/p transistor conducts
somewhere between 0 & 180 degrees of i/p waveform.
D) O/p transistor conducts somewhere between 180 & 360 degrees of i/p waveform.
28. How long will it take to shift an 8-bit number into 8-bit serial in, Parallel out shift register if the clock is set at 10MHZ ?
A) 100ns
B) 900ns
C)800ns
D) 1600ns
29. The drift velocity of electrons, in silicon
A) Is proportional to the
electric field for all values of electric field
B) Is independent of the
electric field
C) Increases at low values
of electric field and decrease at high values of electric field exhibiting
negative differential resistance.
D) Increases linearly with electric field at low values of electric field and gradually saturates at higher values of electric field.
30. The graph shown represents the I-V characteristics of a zener diode. Which part operates as a voltage regulator ?
A) ab
B) bc
C) cd
D) de
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