Intel VLSI Interview Questions

1. Suppose a MOSFET is operating as an amplifier. A 180 degree phase shifted signal between input voltage (Vi) and drain-to-source voltage (VGS) passes through the output coupling capacitor. What will be the consequences ?

a) DC value will be reduced to zero

b) DC value will be reduced to unity

c) DC value will be increases to infinity

d) No change in the DC value

2. A signal is given as x(t) = 12cos(75πt)cos²(100πt). What is the Nyquist sampling rate for the signal?

a) 100 Hz

b) 400 Hz

c) 200 Hz

d) 150 Hz

3. A 4 bit shift register is designed using D FlipFlops in cascade. The outputs are shifted right after each clock pulse. The D FFs are arranged from left to right as D3 D2 D1 and D0. An input x is fed to D3, D1 and x are XORed and fed to D₂ , D0 is complemented and fed to D₁. If the values of x are "11011010", what is the output of the shift register after 4 clock pulses? The initial contents of the register are 1010

a) 1 1 1 0

b) 1 0 1 0

c) 1 1 0 0 

d) 1 0 1 1

4. An analog voltage of the range of -V to +V is required to be converted to N bit 2's complement digital format. If digital value for 0 should be 000 and maximum quantization error should be exceed +/- LSB, determine quantization interval

a) 2V/(2N - 1)

b) 2V/(2N + 1)

c) 2V/(2N - 1)

d) 2V/(2N +1)

5. For a binary weighted resistor Digital to Analog converter, what is the effect of change in resistance of Most Significant Bit (MSB) with respect to resistance of Least Significant Bit (LSB)?

a) Resistance of LSB decreases when the Resistance of MSB changes.

b) Resistance of LSB changes inversely when the Resistance of MSB changes.

c) Resistance of LSB changes when the Resistance of MSB changes with the same amount.

d) Resistance of LSB never changes when the Resistance of MSB changes.

6. On Reset of 8051 of microcontroller, what will be the address of stack pointer? 

a) 00H

b) 01H

c) 07H

d) FFH

7. Find the frequency of oscillations for 8 stage RC phase oscillator. Consider R = 100 Ohm and Capacitor C = 50pF.

a) 4679 KHz

b) 6785 KHz

c) 7960 KHz

d) 9770 KHz

8. An opAmp has a open loop gain of 49. The +ve input is fed with an input voltage of 4.2V and -Ve input is fed with an voltage of 4.1V. What is the output voltage

a) 4.9V

b) 406.7V

c) 205.8V

d) 203.35 V

9. In an RLC series circuit, the impedance at resonance is :

a) Zero

b) R

c) Infinity

d) L/CR

10. What is the status of the signal S0 and S1  when the 8085 microprocessor is in wait states ?

a) 00

b) 01

c) 10

d) 11

11. The contents of PSW( Program Status Word for flag register) for an 8085 microprocessor is 00010101? Then which of the following  flags are set ?

a) Sign, Parity and Carry

b) Auxiliary carry, Sign and Parity

c) Auxiliary Cary, Parity and Carry

d) Sign, Parity and Auxiliary carry

12. If the refractive index of core is n1 and refractive index of cladding is n2 then which one of the given relation exists between n1 and n2 ?

a) n1 = n2

b) n1 > n2

c) n1 < n2

d) n1, n2 = 1

13. Convert the given octal number in to hexadecimal number ?

(255)8

a) 7A

b) FF

c) AD

d) D3

14. For an enhancement type MOSFET, the value of lD(on), VGS(on) and VT(on) are 5mA, 12V and 5V respectively. What is the value of drain current when VGS = 6V ?

a) 2 mA

b) 0.102 mA

c) 5 mA

d) 0.276 mA

15. An 5 input device having A as the MSB and E as LSB has a simplified expression for output as E ⊕ (A + B + C + D). What function is being implemented by the device?

a) Binary to gray converter

b) 5 input 2’s complement

c) 4 input 2’s complement

d) Gray to binary converter

16. Which one of the given options is NOT a part of memory consistency models in computer architecture ?

a) Weak Consistency

b) Sequential Consistency

c) Causal Consistency

d) Entry Consistency

17. On reset of microcontroller 8051 what is the value of SP ?

a) 05H

b) 07H

c) 02H

d) 00H

18. For a General structure of a digital RTL system- define the relation between processing section or Processing unit (PU) and control section or control unit (CU) - 

a) Both Processing unit (PU) and control unit (CU) are separate means both have no relation.

b) Both Processing unit (PU) and control unit (CU) synchronously operating

c) Both Processing unit (PU) and control unit (CU) asynchronously operating

d) Control unit (CU) is a part of Processing unit (PU)

19. What is the speedup of the pipeline for 50 instructions is the length of the execution stages are as given below with instructions latency being 70ns for the pipelined version ?

30 ns, 40ns, 40ns, 50ns, 30ns

a) 2

b) 4

c) 2.5

d) 5

20. For the circuit shown in figure on resistance of M1 as a function of Vg assume UnCox = 50A/V2, W/L = 10, Vth = 0.7V note that the drain terminal is open.

a)

b)

c)

d)

21. Determine the length of the sensitized path of the given RTL combination circuit diagram.

a) Length of the sensitized path = 3

b) Length of the sensitized path = 4

c) Length of the sensitized path = 5

d) Length of the sensitized path = 6

22. For the circuit, if present state is 1, what will the output be for the input  0 0 and 1 1 respectively ?

a) 1 and 1

b) 0 and 0

c) 0 and 1

d) 1 and 0

23. Consider the following figure:

What is the only word it disregards ?

a) 000

b) 100

c) 101

d) 111 

24. The capacitor C1 is 1mFand C0 = 2C1. The inductance is equal to 1mH and resistance is equal to 1KOhm. What is the ratio parallel and series resonance ?

a) √3

b) √(3/2)

c) (√3)/2

d) √4

25. An R-2R ladder network is used to design DAC. For a bit DAC, the reference voltage is 8V and the output voltage is 5.5V. Then what is the input D4D3D2D1D0 ?

a) 10101

b) 10011

c) 10111

d) 10110

26.

a) 001 and 101 are unused

b) 000 and 111 are unused

c) 011 and 100 are unused

d) 011 and 111 are unused

27. A five logic levels RTL circuit diagram and its clock include cycle time is shown in figure-

Define the relationship between cycle time and longest path delay using above circuit diagram.

a) The cycle time (T) is equal to the longest path delay (Tmax)

b) The cycle time (T) cannot be relate to the longest path delay (Tmax)

c) The cycle time (T) cannot be greater to the longest path delay (Tmax)

d) The cycle time (T) cannot be smaller to the longest path delay (Tmax)

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