1. In the circuit shown below, the op amp can be assumed ideal. If Vin(t) is a square wave between -2V and +2V, what is the amplitude of Vo(t)? The diode can be assumed to have a forward drop voltage of 0.7 Volts
a) 3.30
b) 4.00
c) 2.60
d) 0.00
2. A schematic of a buck converter is shown below. Vin is the DC input voltage. CTRL is a control signal that periodically switches ON and OFF. The control loop looks at the output voltage Vo and adjusts the duty cycle of CTRL to change Vo to the desired voltage. If Vo is to be set to 6V, the value of R is gradually increased. What is the lowest value of R at which the inductor current touches 0 during the transient? Assume that the current through the inductor is always higher than 0. Also assume that the capacitor is large enough that Vo is almost constant and switching frequency of CTRL is 1 MHz and L=1 mH Vin = 10 V
a) 500 kOhm
b) 500 Ohm
c) 50 kOhm
d) 5 kOhm
3. Consider a function f(t)=K.u(t) + g(t) where K is an unkown constant. The Laplace transform of g(t) is given by G(s) = 12/[s(s2 + 4s + 3)]. It is also known that f(t) tends to a value equal to 0 as t tends to infinity. What is the value of K?
a) 0
b) -4
c) 12
d) 4
4. In the circuit shown in the figure, what is approximate value of VCE, if VBE for the BJT is 1V ,R1=R2= 1 K Ohm, R3 = 100 K Ohms, VCC= 5 Volts
a) 2 V
b) 6 V
c) 1 V
d) 4 V
5. In the circuit shown in the figure, what is the approximate magnitude of small signal gain Vout/Vin? Assume all the capacitors to be short for the small signal calculations, output Impedance of the transistor to be very high, VT =KT/q=25m, and VBE for the BJT is 1V. R1 = R2 = 2 K Ohm, R3= 200 K Ohms, VCC = 5 Volts
a) 100
b) 60
c) 80
d) 120
6. The op amp shown below is an ideal op amp. If Vin(t)=3.u(t),What is the output time constant in secs?
a) 2
b) 0.5
c) 1
d) 0
7. VIN is connected to a voltage source of 5V. Switches labelled S1 and S2 are kept closed between time 0-1 sec. Switch S3 is turned ON at time=2 sec and remains closed till t=¥. In steady state, at what frequency does the the circuit oscillates if: L=3 µH, C-50 µF
a) Circuit does not have enough energy to be able to oscillate
b) 0.05 Mrad/s
c) 0.08 Mrad/s
d) 0.10 Mrad/s
8. In the below circuit the op amp is ideal. What is the 3-dB bandwidth from Vin(t) to Vo(t)?
a) 2 Mrad/s
b) 1 Mrad/s
c) Infinite
d) 3 Mrad/s
9. A circult connected between nodes A and B has an s-domain transfer function H(s)=B(s)/A(s) with 2 poles and 1 zero. The pole locations in the s-domain are as shown below (at p1 and p2) whereas the location of the zero is at z1. Calculate the 3-dB frequency of the circuit if p1= -10 Mrad/s, z1= +10 Mrad/s and p2=-100 Mrad/s
a) 100 Mrad/s
b) 10 Mrad/s
c) 31.6227766 Mrad/s
d) 1000 Mrad/s
10. In the below circuit, all buffers are ideal and provide a maximum output of 5V. The buffers also provide a signal gain G Among the given choices, at what value of G can the circuit oscillate, if R=20 ohm, C = 1 nF
a) 1
b) 2.5
c) 1.8
d) None of the above
11. The below circuit has 3 capacitors and hence 3 poles. The gain block is an ideal gain block that provides a gain of G=3 between its input and output nodes at all frequencies. For the transfer function Vout(s)/Vin(s), what is the approximate location of the pole (in radians/sec) that is farthest away from the origin in the s-domain if: R = 100 Ohm and C= 2000 pF
a) -5 Mrad/s
b) -50 Mrad/s
c) -500 Mrad/s
12. You are given an N bit base K number Xn-1 Xn-2 Xn-3... X1 X0. You need to convert that number in base K to the corresponding number in base K^2. Which of the following formulas can be applied to convert the N bit number?
a) Summation {(K^2)^((N-2)/2) x (KXm-1 + Xm-2)} where m belongs to N, 1 <m<N
b) Summation { K^ ((N-2)/2) × ( KXm-1 + Xm-2)} where m belongs to N,1<m<N
c) Summation { (K^2)^ (N/2) × ( KXm-1 + Xm-2)} where m belongs to N, 1 < m< N
d) Summation { K^(N/2) x ( KXm-1 + Xm-2) } where m belongs to N, 1<m<N
13. A new type of keyboard is being developed that will have the same functionality as a regular QWERTY keyboard with 104 keys, but with reduced number of keys. Following are some key combinations that will map to a character in this keyboard:
KI+K4+K6 = A
K2+K5+ K3 =B
K2+K5=C
K2 - D
Which of the following digital circuit elements can be used to implement the same?
a) Multiplexer
b) De-Multiplexer
c) Priority Encoder
d) Decoder
14. You have a FIFO architecture, a WRITE system and a READ system. The WRITE system is such that it writes data at the rate of 90 words per 100 clock cycles. The READ system reads at the rate of 4 words per 5 clock cycles. The occurrence of write operation in that time period is guaranteed but their exact distribution among these clock cycles is indeterminate. What should be the depth of the FIFO so that no data is dropped ?
a) 36 words
b) 18 words
c) 9 words
d) Cannot be determined
15. You have been given a large Karnaugh Map. You have to use the K-Map to generate Gray Codes. This can be done by walking the map. However, a Gray Code cannot be generated by random motion on the K-map. Given are a set a rules. Choose the r that one should abide by so that a gray code is generated every time a person walks on the K-Map. Let us say you stand on 0th cell of the Karnaugh Map, then the value generated is 0000 and so on.
A. You can only move horizontally and vertically
B. You cannot finish on the same cell you started from
C. K-Map should exhibit a toroidal feature
a) A,B
b) A,C
c) B,C
d) None of these
16. Given is a MUX based implementation of a digital circuit. You are given the control of the SEL bit. Which of the following is the correct output that will be obtained if the SEL bit is changed first to 0 and then to 1.
a) 0-X^Y^Z
1-XY+Z(X^Y)
b) 0-XY+X(Z^Y)
1-X^Y^Z
c) 0-XY+Z(X^Y)
1-X^Y^Z
d) 0-X^Y^Z
1-ZY+Y(Z^X)
17. Given are two statements S1 and S2. Read the two statements and mark the appropriate option.
S1: The size of the inverters should gradually increase in the design while trying to drive a high capacitive load.
S2: Driving a large inverter directly from the output of a small gate is equivalent to charging and discharging of a large capacitor with a small transistor
a) S1 is correct. S2 is correct. S2 is the correct reason behind S1
b) S1 is correct. S2 is correct. S2 is not the correct reason behind S1
c) S1 is correct. S2 is incorrect
d) S1 is incorrect. S2 is correct.
18. Given are two statements S1 and S2. Read the two statements and mark the appropriate option.
S1: DRAM storage cells can retain their state even after they are powered off and the rate of decay of charge is decreases with decrease in temperature
S2: The leakage current doubles for every 10C Increase in temperature
a) S1 is correct. S2 is correct. S2 is the correct explanation of S1.
b) S1 is correct. S2 is correct. S2 is not the correct explanation of S1.
c) S1 is correct. S2 is incorrect.
d) S1 is incorrect. S2 is correct
19. The following FA circuit CKT is being used to find the sum of the bit of stream that is entered through the two inputs A and B. The initial value of C is 0.
Given are two statements regarding the above scenario. Read the above statements and mark the appropriate option
S1: The circuit takes k clock cycles to to add k bits
S2: We can use a clock with much higher frequency than the typical n-bit adder as there is just one full adder.
a) S1 and S2 are correct and S2 is the correct reason behind S1
b) S1 and S2 are correct but S2 is the incorrect reason behind S1
c) S1 is correct but S2 is incorrect
d) S1 is incorrect but S2 is correct
20. You are given a code snippet in Verilog. You had expected it to be a MUX implementation. However, the synthesis tool that you were using Implemented the same using only AND, OR and NOT gates in a way that it does not form the internal structure of the MUX. How many gates in total will be required to implement the hardware description ?
if (sel_1)
out=1'b1;
else if (sel_2)
out =1'b0:
else
out = inp;
a) 3
b) 4
c) 2
d) 5
21. You are required to write a program to perform the following operations: The program should count the number of 0's in data contained inside a certain register. Among the following operations, which of these is surely required in the implementation of this program?
1:JNZ
2:JC
3:3NC
a) only 1
b) only 1 and 2
c) only 2 and 3
d) None of 1,2 or 3
22. Given is a small code snippet in Verilog which is used to assign variables. Identify the variable that will be assigned last and the time at which assignment will take place during simulation. Assume that the execution of the initial block begins at time t = 0ns. The timescale is 1ns/1ps.
initial
join
a=0;
#20 b=0;
#40 c=0;
#30 d=0;
fork
a) Variable- d
Timestamp- 90ns
b) Variable- d
Timestamp- 30ns
c) Variable- c
Timestamp- 40ns
d) Variable- c
Timestamp- 90ns
23. An integer multiplier takes 2 n-bits inputs from CPU and gives the multiplied output. What number system should be followed by CPU while passing the number to the multiplier, which will result in minimum data bus width (n). Required specification says that numbers to be multiplied can vary from -256 to +255,
a) Signed binary
b) 1's complement
c) 2's complement
d) Both 2 and 3
24. A designer had developed a 3 bit odd parity generator using 2 input nor gate cells only. He designed the circuit in a way so that he will the minimum area. How many cells would he have used?
a) 6
b) 8
c) 10
d) 12
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