1.Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays δ1=2 ns and δ2=4ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0 ns. If the following waveform is applied at input A, how many transition (s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns?
a) 1
b) 4
c) 3
d) 2
2. The logic function f (X, Y) realized by the given circuit is
a) NOR
b) AND
c) NAND
d) XOR
3. A binary down counter consists of four flip-flops. What will be the last output state of the counter before it underflows?
a) 4
b) 0
c) F
d) A
4. Consider the register to register path below. How will you fix the setup violation occurring on point B?
a) Increase delay of dly3
b) Increase hold time of flip flop FF2
c) Increase delay of dly1
d) Increase delay of dly2
5. To correct the shape of square wave with a large slew rate, which logic is more appropriate.
a) Darlington Pair
b) Schmitt trigger
c) D-Flip Flop
d) SR-Flop Flop
6. Below figure shows CMOS implementation of a logic gate.
For gate to have same fall times irrespective of input pattern, what is the sizing requirement of transistor D?
(W/L) of A,B,C =3x and PUN -> Power up network
a) W/L of D=1.5x
b) W/L of D=6x
c) W/L of D=0.6x
d) None of the above
7. The threshold voltage of every NMOS transistor is Vtn. What is the voltage at node "P"?
a) VDD-4Vtn
b) VDD-3Vtn
c) VDD-Vtn
d) VDD-2Vtn
8. How many 2x1 mux are needed to make a 64x1 mux?
a) 31
b) 32
c) 63
d) 64
9. The correct state sequence of the circuit with initial state Q0=1,Q1Q2=0.The state of the circuit is given by the value 4Q2+2Q1+Q0.
a) 1,3,4,6,7,5,2
b) 1,2,5,3,7,6,4
c) 1,2,7,3,5,6,4
d) 1,6,5,7,2,3,4
10. In the given network below, removing which gate would leave the logic unchanged?
a) GATE #1
b) GATE #2
c) GATE #3
d) GATE #4
11. A 256 Mb DRAM chip is organized as a 32M x8 memory externally and as a 16K x16K array internally. Rows must be refreshed at least once every 50 ms to forestall data loss refreshing a row takes 100 ns. Fraction of the total memory bandwidth lost to refresh cycles is.
a) 3.3%
b) 5.2%
c) 7.8%
d) 11.1%
12. All flip flops used have asynchronous reset. Initial state of all flip flops is '0'. The frequency of clock is 45MHz. What is the frequency of Fout?
a) 11.25 MHz with 33% duty cycle
b) 15 MHz with 33% duty cycle
c) 11.25 MHz with 50% duty cycle
d) None of the above
13. Which of the following type counter is more suitable if avoiding errors in continuity is important?
a) Gray code counter
b) Ripple counter
c) Ring counter
d) Johnson counter
14. The 8-input XOR circuit shown has an output of Y=1.Which input combination below(ordered A-H) is correct?
a) 10111100
b) 10111000
c) 11100111
d) 00011101
15. A four variable Boolean function is realized using 4x1 mux as shown in the figure.
The minimized expression for F(U,V,W,X) is
a) (UV+U'V')W'
b) (UV+U'V')(W'X'+W'X)
c) (UV'+U'V)W'
16. What is the maximum allowed clock frequency for the below logic?
a) 1.3/1ns
b) 1/1.3ns
c) 2/1.3ns
d) 1/2.6ns
17. To implement the expression AB'CD + ABC'D + ABCD' it takes
a) one OR gate, three AND gates and three inverters
b) one OR gate, three AND gates and four inverters
c) one OR gate, three AND gates
d) one OR gate, one AND gate
18. What will be Small Signal Gain (Vout/Vin) of this circuit? Assume that the impedance of the current source is infinite.
a) 0
b) infinite
c) gmro
d) ro/R
19. The value of R for which the PMOS transistor in figure will be biased in linear region is
a) 220 Ω
b) 470 Ω
c) 680 Ω
d) 1200 Ω
20. For the AC circuit as shown below, if the rms voltage across the resistor is 120 V, what is the value of the inductor?
a) 0.5 H
b) 0.6 H
c) 1.0 H
d) 1.5 H
21. The voltage e0, indicated in figure has been measured by an ideal voltmeter. Which of the following can be calculated?
a) Blas current of the inverting input only.
b) Blas current of the inverting and non-Inverting inputs only.
c) Input offset current only.
d) Both B & C
22. What is the output resistance looking into the nodes A and B of the circuit shown below
a) ro1+ro2 and 1/gm1gm2ro2
b) 1/gm1 and ro1
c) 1/gm1 and 1/gm1gm2ro2
d) ro1+ro2 and ro1
23. Find the final voltage across C1 when the switch is closed?(Assume C1=C2=C3=C)
a) 3 V
b) 1.5 V
c) 2 V
d) 1 V
24. Refer to the given figure. The roll-off of the circuit shown is about
a) 20 dB/decade
b) 40 dB/decade
c) 60 dB/decade
d) 80 dB/decade
25. Assuming same current flows in both structures shown below(Fig 2a and Fig 2b).
a) The intrinsic gain of Fig 2a > The intrinsic gain of Fig 2b
b) The intrinsic gain of Fig 2b > The intrinsic gain of Fig 2a
c) The intrinsic gains of Fig 2a and Fig 2b are same
d) The minimum allowable voltage to maintain all the transistors in saturation is more in case of Fig 2a than that of Fig 2b
26. An op-amp based circuit is implemented as shown below.
In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node A. connected to the negative input of the op-amp as indicated in the figure is
a) 0.5 V
b) 1 V
c) 0 V
d) -15 V
27. An ideal square wave with period of 20 ms shown in the figure, is passed through an ideal low pass filter with cut-off frequency 120 Hz. Which of the following is an accurate description of the output?
a) Output is zero
b) Output is a triangular waveform with 50Hz frequency
c) Output is a sinusoidal waveform with 50Hz frequency
d) Output is a square waveform with 50Hz frequency and tapered edges
28. The sampling rate for Compact Discs (CDs) is 44,000 samples/s. If the samples are quantized to 256 levels and binary coded, the corresponding bit rate (in bits per second) is
a) 11264000
b) 5500
c) 171.875
d) 352000
29. The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across the diode D1 in steady state
a) cos(wt)-1
b) cos(wt)
c) 1-cos(wt)
d) 1- sin(wt)
30. Consider a MOS structure with equilibrium Fermi potential of the doped silicon substrate is given as 0.3eV. Electron affinity of Si is 4.15eV and metal is 4.1eV. Find the built in potential of the MOS system.
a) -0.8eV
b) 0.8eV
c) 0.9eV
d) -0.9eV
b) 0.8eV
c) 0.9eV
d) -0.9eV
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