1.On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics?
A) Active PMOS load inverter
B) Current source load inverter
C) Push pull inverter
D) None of the above
2.The concentration of hole-electron pairs in pure silicon at T-300 K is 7x10^15per cubic meter Antimony is doped into silicon in a proportion of 1 atom in 10^7 Si atoms Assuming that half of the impurity atoms contribute electron in the conduction band calculate the factor by which the number of charge carriers increases due to doping The number of silicon atoms per cubic meter is 5x10^28.
A) 2.8x10^5
B) 3.1x10^2
C) 4.2x10^5
D) 1.8x10^5
3.We can make 16:1 MUX using (No restriction on number of inputs to each gate)
A) 8AND 1 OR 2 NOT Gates (or) 8,2:1 MUX
B) 20 AND 5 OR and 10 NOT Gates (or) 5, 4:1 MUX
C) 20 AND 10 OR and 10 NOT Gates (or) 6 ,4:1 MUX
D) 16 AND 1 OR and 2 NOT Gates (or) 8, 4:1 MUX
4. As frequency increases:
A) both series and parallel RC impedance decrease
B) series RC impedance decreases and parallel RC impedance increase
C) series RC impedance increases and parallel RC impedance decrease
D) both series and parallel RC impedance increases
5. Transistor works as an open switch when emitter junction is... biased and collector junction is... biased
A) Forward ,forward
B) Reverse, reverse
C) Reverse ,forward
D) Forward, reverse
6. Realization of below Verilog Code will require minimum (Assume, There are no syntax related issues)
module simple_adder (S, C, B1, B2, CLK)
input B1, B2, CLK
output Reg S,C
wire P,Q
P=B1.B2
Q=B1 XOR B2
Always @ CLK
S=Q
C=P
end
end module
A) 3 AND gates , 2 NOT gates , 1 OR Gate,2 Latches
B) 3 AND gates , 2 NOT gates , 1 OR Gate,2 Flops
C) 1 XOR gate, 1 AND gate, 4 Flops
D) 1 XOR gate , 1 AND gate ,4 Latches
7. A 1.5 V battery is connected to 1000 uF capacitor in series with a 150 ohm resistor. How long does the capacitor take to reach a potential of 1 V?
A) 0.05 s
B) 0.1 s
C) 0.15 s
D) 0.2 s
8. Consider the following statements
a. If a copper wire is stretched to make it 0.1% longer, the percentage change in its resistance is 0.1%
b. The random motion of free electrons is due to thermal energy of the conductor
c. Drift velocity of electrons in a conductor increase on increasing the temperature of the conductor
Select the correct answer using the codes below
A) a, b & c
B) a & b
C) b only
D) b & c
9. Which of the following statements is incorrect?
A) The drift current in p-n junction is from the n-side to the p-side
B) Drift Current is due to free electrons only
C) Silicon is preferred over germanium for making semiconductor devices
D) The energy gap in germanium is more than the energy gap in silicon.
10. Consider the following statements:
a) With forward bias to p-n junction , width of depletion layer decrease
b) In an intrinsic semiconductor the number of free electrons equals the number of holes.
Which of the above statements are incorrect.
A) a only
B) b only
C ) Both a and b
D) neither a and b
11. In CMOS circuits which type of the power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?
A) Static dissipation due to transient current and dynamic dissipation . Due to charging and discharging of load capacitance.
B) Dynamic dissipation in both cases
C) Static dissipation in both cases
D) None of the above
12. Pick the correct true(1)/false(0) sequence for below statements:
-Slow gates take up less area than fast gates.
-Worst case rise time for nand2 is when both PMOS are conducting
-Rise time for mirrored XOR is more than AOI-XOR
-NAND gates MUX has better drive capability than transmission gates MUX
A) 1001
B) 1000
C) 0110
D) 0001
13. If a NMOS is operating at following voltages: Vgs=0.6, Vds=0.7, Vt=0.3 voltages and has a Vdsat=0.5 V
i. which fashion does the Ids the drain to source current , varies with Vgs
a) Squared b. linear c. exponential d. Independent of Vgs
ii. Through body biasing if the Vt of the NMOS is changed to 0.6 V, how does the Ids vary in relation to Vds.
a) Squared b. linear c. exponential d. Independent of Vgs
A) a, b
B) b, c
C) c, c
D) a, c
E) a, d
14. For below circuit:
Which of the following is true.
A) If A=0, Q=B+C
B) If A=0 , Q=B.C
C) If A=1, Q=D(BAR)
D) If A=1, Q=D
15. For the circuit given below , the delays of NOR gates , multiplexers and inverters are 2ns, 1.5ns and 1ns. If all the inputs are applied at the same time instant, maximum propagation delay (in ns) of the following circuit is:
A) 5 ns
B) 4.5 ns
C) 6 ns
D) 8.5 ns
16. What is the setup and hold time of the SR flip-flop given below.
A) I1+I2+I3+T1, I3+I4
B) I1+I3+T1, 0
C) I4+I1+T1, I3+I4
D) I1+I2+I3+T1, 0
E) Its not SR flip flop.
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